UPSTREAM: intel/gma: Fix typo GMBUS0 -> GMBUS1 in edid.c

This typo existed in code before rewriting for using
defines and it's clearly visible after rewrite.
Previously it was writing to reserved area of GMBUS0 register,
while values are matching those of GMBUS1.

This line probably is a no-op since it's just sending the STOP
again (without an address set this time).

BUG=none
BRANCH=none
TEST=none

Change-Id: I7bcbaff545f45f0bcb6c23d7f4496f10681ef2eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 34e10871f9
Original-Change-Id: Ic85ef925c41ad01ed469f9d4f4412cbe44ca6d8e
Original-Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/16341
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/524605
This commit is contained in:
Sebastian "Swift Geek" Grzywna 2016-09-08 02:05:31 +02:00 committed by chrome-bot
commit 4f84d58741

View file

@ -56,7 +56,7 @@ static void intel_gmbus_stop_bus(u8 * mmio, u8 bus)
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE
| (AT24_ADDR << 1) );
wait_rdy(mmio);
write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);
write32(GMBUS2_ADDR, GMBUS_INUSE);
}
@ -101,7 +101,7 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
| GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP
| (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
wait_rdy(mmio);
write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP );
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP );
write32(GMBUS2_ADDR, GMBUS_INUSE);
printk (BIOS_SPEW, "EDID:\n");