From 4e72de622109e8b134a75826baee11291a1c7204 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 16 Jul 2013 09:01:43 -0700 Subject: [PATCH] lynxpoint: power management setup tweak Updated from 161 ref code BUG=chrome-os-partner:20972 BRANCH=falco TEST=emerge-falco chromeos-coreboot-falco Change-Id: I3e07935fec1df21f14d97d165792fe54bf9e474c Reviewed-on: https://gerrit.chromium.org/gerrit/62128 Tested-by: Duncan Laurie Reviewed-by: Aaron Durbin Reviewed-by: Stefan Reinauer Commit-Queue: Duncan Laurie --- src/southbridge/intel/lynxpoint/lpc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 1736466a7f..a92b0c6eed 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -474,13 +474,12 @@ static void enable_lp_clock_gating(device_t dev) * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 * RCBA + 0x2614[23:16] = 0x20 * RCBA + 0x2614[30:28] = 0x0 - * RCBA + 0x2614[26] = 1 (IF B2 STEP && 0:31.0@0xFA > 4) + * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) */ RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ - if (pch_silicon_revision() >= LPT_LP_STEP_B2 && - pci_read_config8(dev, 0xfa) > 4) + if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b) RCBA32_OR(0x2614, (1<<26)); RCBA32_OR(0x900, 0x0000031f);