diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb
index 623c5a196c..f687f02f1f 100644
--- a/src/mainboard/google/nyan/devicetree.cb
+++ b/src/mainboard/google/nyan/devicetree.cb
@@ -28,6 +28,8 @@ chip soc/nvidia/tegra124
 	register "display_controller" = "TEGRA_ARM_DISPLAYA"
 	register "xres" = "2560"
 	register "yres" = "1700"
+	# this setting is what nvidia does; it makes no sense
+	# and does not agree with hardware. Why'd they do it?
 	register "framebuffer_bits_per_pixel" = "24"
 	register "cache_policy" = "DCACHE_WRITETHROUGH"
 
@@ -67,4 +69,7 @@ chip soc/nvidia/tegra124
 	register "vfront_porch" = "3"
 	register "vsync_width" = "10"
 	register "vback_porch" = "36"
+
+	# we *know* the pixel clock for this system.
+	register "pixel_clock" = "285"
 end
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c
index bb63f4605a..31daa3a94a 100644
--- a/src/soc/nvidia/tegra124/display.c
+++ b/src/soc/nvidia/tegra124/display.c
@@ -87,7 +87,7 @@ static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
 };
 
 static int update_display_mode(struct dc_disp_reg *disp,
-							   struct soc_nvidia_tegra124_config *config)
+			       struct soc_nvidia_tegra124_config *config)
 {
 	u32 val;
 	u32 rate;