diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 9d05ee46ea..93be1b434b 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -55,6 +55,7 @@ romstage-y += thermal.c
 romstage-y += thermal_sram.c
 
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
+ramstage-y += dcc.c
 ramstage-y += ddp.c
 ramstage-y += ../common/display.c
 ramstage-y += ../common/dpm_v2.c
diff --git a/src/soc/mediatek/mt8196/dcc.c b/src/soc/mediatek/mt8196/dcc.c
new file mode 100644
index 0000000000..13a621c5b3
--- /dev/null
+++ b/src/soc/mediatek/mt8196/dcc.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/dcc.h>
+
+void dcc_init(void)
+{
+	/* DSU */
+	clrbits32p(BUS_PLLDIV_CFG1, GENMASK(20, 16));
+	/* LCPU */
+	clrbits32p(CPU_PLLDIV_0_CFG1, GENMASK(20, 16));
+	/* MCPU */
+	clrsetbits32p(CPU_PLLDIV_1_CFG1, GENMASK(20, 16), BIT(20) | GENMASK(18, 16));
+	/* BCPU */
+	clrsetbits32p(CPU_PLLDIV_2_CFG1, GENMASK(20, 16), GENMASK(17, 16) | GENMASK(20, 19));
+
+	printk(BIOS_DEBUG, "[DCC] DSU=%#x, LCPU=%#x, MCPU=%#x, BCPU=%#x\n",
+	       (read32p(BUS_PLLDIV_CFG1) >> 16) & 0x1F,
+	       (read32p(CPU_PLLDIV_0_CFG1) >> 16) & 0x1F,
+	       (read32p(CPU_PLLDIV_1_CFG1) >> 16) & 0x1F,
+	       (read32p(CPU_PLLDIV_2_CFG1) >> 16) & 0x1F);
+}
diff --git a/src/soc/mediatek/mt8196/include/soc/dcc.h b/src/soc/mediatek/mt8196/include/soc/dcc.h
new file mode 100644
index 0000000000..3aba1f1d1c
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/dcc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_MT8196_DCC_H
+#define SOC_MEDIATEK_MT8196_DCC_H
+
+#include <soc/addressmap.h>
+
+#define BUS_PLLDIV_CFG1		(MCUSYS_BASE + 0x0104) /* DSU */
+#define CPU_PLLDIV_0_CFG1	(MCUSYS_BASE + 0x0110) /* LCPU */
+#define CPU_PLLDIV_1_CFG1	(MCUSYS_BASE + 0x011C) /* MCPU */
+#define CPU_PLLDIV_2_CFG1	(MCUSYS_BASE + 0x0128) /* BCPU */
+
+void dcc_init(void);
+
+#endif /* SOC_MEDIATEK_MT8196_DCC_H */
diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c
index 2d32bc3d45..c5a83d0c73 100644
--- a/src/soc/mediatek/mt8196/soc.c
+++ b/src/soc/mediatek/mt8196/soc.c
@@ -3,6 +3,7 @@
 #include <bootmem.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <soc/dcc.h>
 #include <soc/dramc_info.h>
 #include <soc/emi.h>
 #include <soc/gpueb.h>
@@ -52,6 +53,7 @@ static void soc_init(struct device *dev)
 {
 	uint32_t storage_type = mainboard_get_storage_type();
 
+	dcc_init();
 	mtk_fsp_init(RAMSTAGE_SOC_INIT);
 	mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, sizeof(storage_type), &storage_type);
 	add_pi_image_params();