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UPSTREAM: skylake: Add GPIO macro for configuring inverted APIC input

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Add a GPIO macro that allows a pin to be routed to the APIC with
the input inverted.  This allows a normal interrupt to get used as
a GPE during firmware and still be used as a perhiperal interrupt
in the kernel.

BUG=chrome-os-partner:58666
BRANCH=None

TEST=boot en eve and use TPM IRQ in firmware and OS

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17176
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96
Reviewed-on: https://chromium-review.googlesource.com/404975
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2016-10-28 09:07:49 -07:00 • committed by chrome-bot
commit 4b058d165f
1 changed files with 6 additions and 0 deletions
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6
src/soc/intel/skylake/include/soc/gpio.h
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@ -144,6 +144,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
_PAD_CFG(pad_, term_, \
_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES))
/* General purpose input passed through to IOxAPIC as inverted input. */
#define PAD_CFG_GPI_APIC_INVERT(pad_, term_, rst_) \
_PAD_CFG(pad_, term_, \
_DW0_VALS(rst_, RAW, NO, LEVEL, NO, YES, YES, NO, NO, NO, GPIO, NO, \
YES))
/* General purpose input routed to SCI. This assumes edge triggered events. */
#define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \
_PAD_CFG_ATTRS(pad_, term_, \