From 4b058d165f9989316dadfe10e5d4aedc48b1e8f5 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 28 Oct 2016 09:07:49 -0700 Subject: [PATCH] UPSTREAM: skylake: Add GPIO macro for configuring inverted APIC input Add a GPIO macro that allows a pin to be routed to the APIC with the input inverted. This allows a normal interrupt to get used as a GPE during firmware and still be used as a perhiperal interrupt in the kernel. BUG=chrome-os-partner:58666 BRANCH=None TEST=boot en eve and use TPM IRQ in firmware and OS Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/17176 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96 Reviewed-on: https://chromium-review.googlesource.com/404975 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/include/soc/gpio.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index d86af0f54a..dd9b9a340c 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -144,6 +144,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); _PAD_CFG(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES)) +/* General purpose input passed through to IOxAPIC as inverted input. */ +#define PAD_CFG_GPI_APIC_INVERT(pad_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, YES, YES, NO, NO, NO, GPIO, NO, \ + YES)) + /* General purpose input routed to SCI. This assumes edge triggered events. */ #define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \ _PAD_CFG_ATTRS(pad_, term_, \