erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Broadwell: Pass TSC value to romstage_main

Browse source 
The romstage_main routine takes three parameters: bist, tsc_low and
tsc_hi.  However in cache_as_ram.inc only the bist value is being
passed.  This patch adds the two halves of the TSC value.

BRANCH=none
BUG=None
TEST=Build and run on Samus

Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: de565f28dc
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e
Original-Reviewed-on: https://chromium-review.googlesource.com/231173
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9280
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Lee Leahy 2014-11-20 16:56:44 -08:00 • committed by Patrick Georgi
commit 4a69c34d54
1 changed files with 6 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/soc/intel/broadwell/romstage/cache_as_ram.inc
View file

@ -180,7 +180,13 @@ clear_mtrrs:
/* Restore the BIST result. */
movl %ebp, %eax
/* Build the call frame. */
movl %esp, %ebp
movd %mm1, %ebx
pushl %ebx
movd %mm0, %ebx
pushl %ebx
pushl %eax
before_romstage: