From 49a257a7db8fb6245bc63d0bd06f56a16c4789e4 Mon Sep 17 00:00:00 2001 From: Tongtong Pan Date: Tue, 8 Apr 2025 20:51:10 +0800 Subject: [PATCH] mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ Use GPP_E03 as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. BUG=b:403383143 Test=emerge-fatcat coreboot and Confirm the log: cros_ec_lpcs GOOG0004:00: Chrome EC device registered Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14 Signed-off-by: Tongtong Pan Reviewed-on: https://review.coreboot.org/c/coreboot/+/87210 Reviewed-by: Kapil Porwal Reviewed-by: Jayvik Desai Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Weimin Wu --- .../fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h | 2 +- src/mainboard/google/fatcat/variants/felino/gpio.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h index dc4ce13185..067c361161 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -26,7 +26,7 @@ /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_F23 #elif CONFIG(BOARD_GOOGLE_FELINO) - #define EC_SYNC_IRQ 0 /* TODO */ + #define EC_SYNC_IRQ GPP_E03_IRQ #define GPIO_PCH_WP 0 /* TODO */ /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_D03 diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index a70e9fe09f..a7df5fccb7 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -206,8 +206,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_E01, NONE, PLTRST), /* GPP_E02: NC */ PAD_NC(GPP_E02, NONE), - /* GPP_E03: NC */ - PAD_NC(GPP_E03, NONE), + /* GPP_E03: EC_SYNC_IRQ */ + PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), /* GPP_E05: NC */ PAD_NC(GPP_E05, NONE), /* GPP_E06: GPP_E06 */