From 4973c2e60b859640782069e81fffe160607b65f3 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 24 Aug 2016 08:49:29 -0500 Subject: [PATCH] UPSTREAM: soc/intel/skylake: align chromium Chrome OS config The chromium tree is currently using a different config for Chrome OS than what is being built in coreboot.org. Align those settings to reflect how skylake Chrome OS boards are actually shipped to provide proper parity between coreboot.org and chromium. CQ-DEPEND=CL:374980,CL:37336 BUG=None BRANCH=None TEST=None Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/16313 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Paul Menzel Change-Id: I7ab9c1dfa8c6be03ac2125fb06cb7022f3befa97 Reviewed-on: https://chromium-review.googlesource.com/374981 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/Kconfig | 2 ++ src/soc/intel/skylake/Makefile.inc | 1 + 2 files changed, 3 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 235f8620c6..ef3f156da2 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -56,9 +56,11 @@ config CPU_SPECIFIC_OPTIONS config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC + select SEPARATE_VERSTAGE select VBOOT_EC_SLOW_UPDATE select VBOOT_OPROM_MATTERS select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH select VIRTUAL_DEV_SWITCH diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index b92eab317f..716c3d503f 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -28,6 +28,7 @@ bootblock-y += pmutil.c bootblock-y += tsc_freq.c verstage-y += flash_controller.c +verstage-y += monotonic_timer.c verstage-y += pch.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c