From 43abed730f222c8a685c250a58c981268994a65d Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 25 Nov 2013 20:10:11 -0800 Subject: [PATCH] nyan: change devicetree for the new display settings. These panel numbers provided by the OEM. The old display will stop working. BUG=None TEST=builds. I'll test when I get a unit. BRANCH=None Change-Id: I6020f0c725d44c4b69d5806e0dfc8da125686baf Signed-off-by: Ronald G. Minnich Reviewed-on: https://chromium-review.googlesource.com/177958 Reviewed-by: David Hendricks Commit-Queue: Ronald Minnich Tested-by: Ronald Minnich --- src/mainboard/google/nyan/devicetree.cb | 27 +++++++++++++++---------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index f687f02f1f..8abc187d55 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -26,8 +26,8 @@ chip soc/nvidia/tegra124 # are no single-access resources such as the infamous # cf8/cfc registers found on PCs. register "display_controller" = "TEGRA_ARM_DISPLAYA" - register "xres" = "2560" - register "yres" = "1700" + register "xres" = "1366" + register "yres" = "768" # this setting is what nvidia does; it makes no sense # and does not agree with hardware. Why'd they do it? register "framebuffer_bits_per_pixel" = "24" @@ -59,17 +59,22 @@ chip soc/nvidia/tegra124 #V sync = 1713 - 1703 = 10 #V back porch = 1749 - 1713 = 36 #href_to_sync and vref_to_sync are from the vendor - - register "href_to_sync" = "11" - register "hfront_porch" = "48" - register "hsync_width" = "32" - register "hback_porch" = "80" +#this is just an example for a Pixel panel; other panels differ. +# Here is a peppy panel: +# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred +# h: width 1366 start 1502 end 1532 total 1592 +# v: height 768 start 776 end 788 total 800 +# These numbers were provided by Nvidia. + register "href_to_sync" = "1" + register "hfront_porch" = "44" + register "hsync_width" = "46" + register "hback_porch" = "44" register "vref_to_sync" = "1" - register "vfront_porch" = "3" - register "vsync_width" = "10" - register "vback_porch" = "36" + register "vfront_porch" = "6" + register "vsync_width" = "8" + register "vback_porch" = "6" # we *know* the pixel clock for this system. - register "pixel_clock" = "285" + register "pixel_clock" = "71" end