Enable IDE (courtesy Adam Agnew and Tiara)
This commit is contained in:
Ronald G. Minnich
parent
844133bfd0
commit
425d4ccc14
1 changed files with 114 additions and 0 deletions
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@ -18,6 +18,116 @@ static char rcsid[] =
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#include <pci_ids.h>
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#include <cpu/p5/io.h>
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#include <types.h>
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/*
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* Something in the pci enumerator appears to be hosing
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* values in the ide pci space. This is a temp workaround.
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*/
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#define BYTE sizeof(u8)
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#define WORD sizeof(u16)
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#define DBLE sizeof(u32)
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#define IDE_REG_EXTENDED_OFFSET (0x200u)
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#define IDE_REG_SECTOR_COUNT(base) ((base) + 2u)
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#define IDE_REG_CONTROL(base) ((base) + IDE_REG_EXTENDED_OFFSET + 6u)
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#define IDE_BASE1 (0x1F0u) /* primary controller */
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#define ASIZE(x) (sizeof(x)/sizeof((x)[0]))
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void ide_fixup(void) {
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volatile int delay;
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struct pci_dev *dev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, (void *)NULL);
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int i;
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u8 val8;
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u16 val16;
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u32 val32;
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typedef struct {
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u8 size;
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u8 regno;
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u32 andval;
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u32 orval;
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} initreg_t;
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static const initreg_t ide_init[] = {
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/*
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* BUS(0), DEVICE(0), FUNCTION(1): IDE Interface. Bridge
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*/
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/*SIZE REG AND-MASK OR-MASK */
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{ WORD, 0x04, 0x0, 0x0007 }, /* Command Register. sets mem+ */
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{ WORD, 0x06, 0x0, 0x3000 }, /* Status reg, clear aborts. */
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{ WORD, 0x09, 0x0A, 0x00 }, /* Programming interface = Compatible mode. */
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{ BYTE, 0x0D, 0x0, 0x10 }, /* Latency Timer */
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/* We let the pci enumerator assign these. */
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// { DBLE, 0x10, 0x0, 0x1F1 }, /* Primary channel base addr. */
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// { DBLE, 0x14, 0x0, 0x3F5 }, /* Primary channel control base addr. */
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// { DBLE, 0x18, 0x0, 0x171 }, /* Secondary channel base addr. */
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// { DBLE, 0x1C, 0x0, 0x375 }, /* Secondary channel control base addr. */
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// { DBLE, 0x20, 0x0, 0x4001 }, /* Control register base addr. */
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{ WORD, 0x2C, 0x0, 0x1039 }, /* Subsystem vendor ID. */
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{ WORD, 0x2E, 0x0, 0x5513 }, /* Subsystem ID. */
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{ BYTE, 0x3c, 0x0, 0x0e }, /* reserved don't do this, sets irq 14 */
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{ BYTE, 0x40, 0x00, 0x01 }, /* Primary master data recovery time. */
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{ BYTE, 0x41, 0x00, 0xb3 }, /* Primary master data active time. UDMA */
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{ BYTE, 0x42, 0x00, 0x00 }, /* Primary slave data recovery time. */
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{ BYTE, 0x43, 0x00, 0x00 }, /* Primary slave data active time. */
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{ BYTE, 0x44, 0x00, 0x00 }, /* Secondary master data recovery time. */
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{ BYTE, 0x45, 0x00, 0x00 }, /* Secondary master data active time. */
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{ BYTE, 0x46, 0x00, 0x00 }, /* Secondary slave data recovery time. */
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{ BYTE, 0x47, 0x00, 0x00 }, /* Secondary slave data active time. */
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{ BYTE, 0x48, 0x00, 0x05 }, /* Ide status */
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{ BYTE, 0x4A, 0x40, 0xe6 }, /* Ide general control 0 was 0x62 */
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{ BYTE, 0x4B, 0x00, 0x11 }, /* Ide general control 1 */
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{ WORD, 0x4C, 0x00, 0x0200}, /* prefetch of primary. */
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{ WORD, 0x4E, 0x00, 0x0200} /* prefetch of secondary. */
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//{ BYTE, 0x48, 0x00, 0x33 }, /* Ide status */
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//{ BYTE, 0x4A, 0x00, 0xe2 }, /* Ide general control 0 was 0x62 */
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//{ BYTE, 0x4B, 0x00, 0x00 } /* Ide general control 1 */
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/* The following register has recommended setting of 0x41 in 630 programming guide,
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* But no documentation in the manual. It looks identical to the same register in the
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* 530.
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*/
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,
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{ BYTE, 0x52, 0xFF, 0x14 } /* Miscelaneous control (Only Doc). */
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};
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int initlen=ASIZE(ide_init);
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const initreg_t * inittab = ide_init;
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printk_info ("Entering the initregs process\n");
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for (i = 0; i < initlen; ++i) {
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u16 regno = inittab[i].regno;
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switch (inittab[i].size) {
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case BYTE:
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pci_read_config_byte(dev, regno, &val8);
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val8 = (val8 & inittab[i].andval) | inittab[i].orval;
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pci_write_config_byte(dev, regno, val8);
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break;
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case WORD:
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pci_read_config_word(dev, regno, &val16);
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val16 = (val16 & inittab[i].andval) | inittab[i].orval;
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pci_write_config_word(dev, regno, val16);
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break;
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case DBLE:
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pci_read_config_dword(dev, regno, &val32);
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val32 = (val32 & inittab[i].andval) | inittab[i].orval;
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break;
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default:
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outb_p(0xEE,0x80);
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while(1);
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break;
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}
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}
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}
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void keyboard_on()
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{
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u8 regval;
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@ -35,6 +145,7 @@ void keyboard_on()
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pc_keyboard_init();
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}
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void nvram_on()
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{
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struct pci_dev *pcidev;
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@ -90,6 +201,7 @@ serial_irq_fixedup(void)
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}
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}
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/* apc_fixup: Fix up the Mux-ed GPIO Lines controlled by APC registers
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*
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* For SiS630A/B Mainboards, the MAC address of the internal SiS900 is stored in EEPROM
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@ -255,6 +367,7 @@ acpi_fixup(void)
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void
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final_southbridge_fixup()
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{
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#ifdef OLD_KERNEL_HACK
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struct pci_dev *pcidev;
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@ -293,6 +406,7 @@ final_southbridge_fixup()
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apc_fixup();
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serial_irq_fixedup();
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acpi_fixup();
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ide_fixup();
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printk_debug("Southbridge fixup done for SIS 503\n");
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}
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