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Add support for the s1846 440BX mainboard.

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This commit is contained in:
Ronald G. Minnich 2001-09-30 04:55:42 +00:00
commit 844133bfd0
6 changed files with 564 additions and 0 deletions
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26
src/mainboard/tyan/s1846/Config Normal file
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arch i386
mainboardinit cpu/i386/entry16.inc
ldscript cpu/i386/entry16.lds
mainboardinit cpu/i386/reset16.inc
ldscript cpu/i386/reset16.lds
mainboardinit superio/NSC/pc87309/setup_serial.inc
mainboardinit pc80/serial.inc
northbridge intel/440bx
southbridge intel/piix4e
mainboardinit cpu/p6/earlymtrr.inc
superio NSC/pc87309
option ENABLE_FIXED_AND_VARIABLE_MTRRS
option PIIX4_DEVFN=0x38
option NO_KEYBOARD
option ZKERNEL_START=0xfffc0000
option ZKERNEL_MASK=0x7f
option L440BX
object mainboard.o
cpu p6
cpu p5

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src/mainboard/tyan/s1846/Makefile Normal file
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CPUFLAGS=-DL440BX -Di686 -Di586 -DINTEL_BRIDGE_CONFIG -DPIIX4E_NVRAM
CPUFLAGS += -D__KERNEL__
CPUFLAGS += -DINTEL_PPRO_MTRR -DPIIX4E_KEYBOARD
CPUFLAGS += -DSMP
#CPUFLAGS += -DHAVE_FRAMEBUFFER
CPUFLAGS += -DNEWPCI
CPUFLAGS += -DZKERNEL_START=0xfff40000
CPUFLAGS += -DZKERNEL_MASK=0x3ed
CPUFLAGS += -DSERIAL_CONSOLE
CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 debug 3 single"'
CPUFLAGS += -DPIIX4_DEVFN=0x90
#CPUFLAGS += -DUPDATE_MICROCODE
phlash_floppy: phlash
mcopy -o /tmp/$(PHLASH_BASE_NAME).bi? a:
crt0.s: crt0.S ../../chip/intel/intel_start32.S ../../chip/intel/intel_440ram-2.S
include ../Makefile.common
# here begins stupid stuff for the phlash program. It's ugly.
#PHLASH_BASE_NAME=p11-0105
PHLASH_BASE_NAME=p11-0102
#PHLASH_BASE_NAME=p12-0115
#PHLASH_BASE_NAME=p13-0125
phlash: vmlinux.bin.gz linuxbios.rom headers
rm -f xa?
split -b 64k vmlinux.bin.gz
# Now just touch them if we have a really
# small kernel!
touch xaa xab xac xad xae xaf xag xah
# this if starting at bank 4, and proceeding on. Unused banks are dups
# intel nvram is odd all of the banks are byte swapped
cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1
cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3
cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2
cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4
cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7
cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6
cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9
cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8
cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia
# Part o & 5 seem not to be written reliably for some reason...
cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio
cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5
sh -x BUILD_PHLASH_FILES $(PHLASH_BASE_NAME)
headers: \
$(PHLASH_BASE_NAME).bi1.header \
$(PHLASH_BASE_NAME).bi2.header \
$(PHLASH_BASE_NAME).bi3.header \
$(PHLASH_BASE_NAME).bi4.header \
$(PHLASH_BASE_NAME).bi5.header \
$(PHLASH_BASE_NAME).bi6.header \
$(PHLASH_BASE_NAME).bi7.header \
$(PHLASH_BASE_NAME).bi8.header \
$(PHLASH_BASE_NAME).bi9.header \
$(PHLASH_BASE_NAME).bia.header \
$(PHLASH_BASE_NAME).bio.header
# This builds the headers from the intel flash disk.
# we are not distributing this disk; you need to get it.
BUILDHEADER=dd if=$< of=$@ bs=1 count=160
$(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia
$(BUILDHEADER)
$(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio
$(BUILDHEADER)
clean::
rm -f $(PHLASH_BASE_NAME)*

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src/mainboard/tyan/s1846/crt0.S Normal file
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/*
* $ $
*
*/
#include <asm.h>
#include <intel.h>
#include <pciconf.h>
/*
* This is the entry code (the mkrom(8) utility makes a jumpvector
* to this adddess.
*
* When we get here we are in x86 real mode.
*
* %cs = 0xf000 %ip = 0x0000
* %ds = 0x0000 %es = 0x0000
* %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6,
* where x is undefined)
* %fl = 0x0002
*/
.text
.code16
#include <cpu/p5/start32.inc>
#include <pc80/i8259.inc>
#include <superio/NSC/pc87309/setup_serial.inc>
#include <pc80/serial.inc>
TTYS0_TX_STRING($ttyS0_test)
/* initialize the RAM */
/* different for each motherboard */
#include <northbridge/intel/440bx/raminit.inc>
#include <sdram/generic_sdram.inc>
#undef RAMTEST
#ifdef RAMTEST
#include <ram/ramtest.inc>
#include <cpu/p6/earlymtrr.inc>
movl $0x00000000, %eax
movl $0x0009ffff, %ebx
movl $24,%ecx
CALLSP(ramtest)
#if 0
movl $0x08000000, %eax
movl $0x08001000, %ebx
movl $24,%ecx
CALLSP(ramtest)
movl $0x10000000, %eax
movl $0x10001000, %ebx
movl $24,%ecx
CALLSP(ramtest)
#endif
#endif
/*
* Copy data into RAM and clear the BSS. Since these segments
* isn't really that big we just copy/clear using bytes, not
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
TTYS0_TX_STRING($str_after_ram)
cld /* clear direction flag */
leal EXT(_ldata), %esi
leal EXT(_data), %edi
movl $EXT(_eldata), %ecx
subl %esi, %ecx
jz .Lnodata /* should not happen */
rep
movsb
.Lnodata:
intel_chip_post_macro(0x12) /* post 12 */
TTYS0_TX_STRING($str_after_copy)
/** clear stack */
xorl %edi, %edi
movl $_PDATABASE, %ecx
xorl %eax, %eax
rep
stosb
/** clear bss */
leal EXT(_bss), %edi
movl $EXT(_ebss), %ecx
subl %edi, %ecx
jz .Lnobss
xorl %eax, %eax
rep
stosb
.Lnobss:
/*
* Now we are finished. Memory is up, data is copied and
* bss is cleared. Now we call the ``main´´ routine and
* let it do the rest.
*/
intel_chip_post_macro(0xfe) /* post fe */
TTYS0_TX_STRING($str_pre_main)
/* set new stack */
movl $_PDATABASE, %esp
/* memory is up. Let's do the rest in C -- much easier. */
call EXT(intel_main)
/*NOTREACHED*/
.Lhlt: hlt
jmp .Lhlt
ttyS0_test: .string "\r\n\r\nHello world!!! I am here\r\n"
str_after_ram: .string "Ram Initialize?\r\n"
str_after_copy: .string "after copy?\r\n"
str_pre_main: .string "before main\r\n"
newline: .string "\r\n"

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src/mainboard/tyan/s1846/ldscript.ld Normal file
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/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*
* $Id$
*
*/
/* oh, barf. This won't work if all you use is .o's. -- RGM */
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
*/
/*
* We use ELF as output format. So that we can
* debug the code in some form.
*/
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
/*
* Memory map:
*
* 0x00000 (4*4096 bytes) : stack
* 0x04000 (4096 bytes) : private data
* 0x05000 : data space
* 0x90000 : kernel stack
* 0xf0000 (64 Kbyte) : EPROM
*/
MEMORY
{
ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is
* max for STPC */
rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */
}
_PDATABASE = 0x04000;
_RAMBASE = 0x05000;
_KERNSTK = 0x90000;
/* should be parameterized but is not, yuck! */
/*
_ROMBASE = 0xe0000;
*/
_ROMBASE = 0xf0000;
/*
* Entry point is not really nececary, since the mkrom(8)
* tool creates a entry point that jumps to $0xc000:0x0000.
*/
/* baloney, but ... RGM*/
ENTRY(_start)
SECTIONS {
/*
* First we place the code and read only data (typically const declared).
* This get placed in rom.
*/
.text _ROMBASE : {
_text = .;
*(.text);
*(.rodata);
_etext = .;
}
_pdata = .;
/*
.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +
SIZEOF(.rodata)) {
*/
.pdata _PDATABASE : AT ( _etext ) {
*(.pdata);
}
_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
/*
* After the code we place initialized data (typically initialized
* global variables). This gets copied into ram by startup code.
* __data_start and __data_end shows where in ram this should be placed,
* whereas __data_loadstart and __data_loadend shows where in rom to
* copy from.
*/
.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
_data = .;
*(.data)
*(.sdata)
*(.sdata2)
*(.got)
_edata = .;
}
_ldata = LOADADDR(.data);
_eldata = LOADADDR(.data) + SIZEOF(.data);
/*
* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between __bss_start and __bss_end with zeroes.
*/
.bss ( ADDR(.data) + SIZEOF(.data) ) : {
_bss = .;
*(.bss)
*(.sbss)
*(COMMON)
_ebss = .;
_heap = .;
}
}
/*
* This provides the start and end address for the whole image
*/
_image = LOADADDR(.text);
_eimage = LOADADDR(.data) + SIZEOF(.data);
/* EOF */

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src/mainboard/tyan/s1846/mainboard.c Normal file
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#include <printk.h>
#include <pci.h>
#include <cpu/p5/io.h>
// this needs to be moved about a bit to northbridge.c etc.
void mainboard_fixup()
{
struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev;
unsigned smbus_io, pm_io;
unsigned int i, j;
printk_debug("intel_mainboard_fixup()\n");
#if 1
pm_pcidev = pci_find_device(0x8086, 0x7113, 0);
nic_pcidev = pci_find_device(0x8086, 0x1229, 0);
host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
#endif
#if 1
pci_write_config_byte(nic_pcidev, 0x3c, 21);
#endif
#if 1
{
u8 byte;
u16 word;
u32 dword;
for(i = 0; i < 8; i++) {
pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte);
printk_debug("DRB[i] = 0x%02x\n", byte);
}
pci_read_config_byte(host_bridge_pcidev, 0x57, &byte);
printk_debug("DRAMC = 0x%02x\n", byte);
pci_read_config_byte(host_bridge_pcidev, 0x74, &byte);
printk_debug("RPS = 0x%02x\n", byte);
pci_read_config_word(host_bridge_pcidev, 0x78, &word);
printk_debug("PGPOL = 0x%04x\n", word);
pci_read_config_dword(host_bridge_pcidev, 0x50, &dword);
printk_debug("NBXCFG = 0x%04x\n", dword);
}
#endif
#if 1
printk_debug("Reset Control Register\n");
outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9);
printk_debug("port 92\n");
outb((inb(0x92) & 0xFE), 0x92);
printk_debug("Disable Nmi\n");
outb(0, 0x70);
printk_debug("enabling smbus\n");
#if 0
smbus_io = NewPciIo(0x10);
#else
smbus_io = 0xFFF0;
#endif
pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */
pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */
pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */
printk_debug("enable pm functions\n");
#if 0
pm_io = NewPciIo(0x40);
#else
pm_io = 0xFF80;
#endif
pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */
pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */
printk_debug("disabling smi\n");
/* GLBEN */
outw(0x00, pm_io + 0x20);
/* GLBCTL */
outl((1 << 24), pm_io + 0x28);
printk_debug("Disable more pm stuff\n");
/* PMEN */
outw((1 << 8), pm_io + 0x02);
/* PMCNTRL */
outw((0x5 << 10) , pm_io + 0x4);
/* PMTMR */
outl(0, pm_io + 0x08);
/* GPEN */
outw(0, pm_io + 0x0e);
/* PCNTRL */
outl(0, pm_io + 0x10);
/* GLBSTS */
/* DEVSTS */
/* GLBEN see above */
/* GLBCTL see above */
/* DEVCTL */
outl(0, pm_io + 0x2c);
/* GPIREG */
/* GPOREG */
printk_debug("Set the subsystem vendor id\n");
pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086);
printk_debug("Disabling pm stuff in pci config space\n");
#define MAX_COUNTERS
#ifndef MAX_COUNTERS
/* counters to 0 */
#define WHICH_COUNTERS(min,max) min
#else
/* max out the counters */
#define WHICH_COUNTERS(min,max) max
#endif
/* CNTA */
pci_write_config_dword(pm_pcidev, 0x44, WHICH_COUNTERS(0x004000f0, 0xFFFFFFFF));
/* CNTB */
pci_write_config_dword(pm_pcidev, 0x48, WHICH_COUNTERS(0x00000400, 0x007c07df));
/* GPICTL */
pci_write_config_dword(pm_pcidev, 0x4c, 0);
/* DEVRESD */
pci_write_config_dword(pm_pcidev, 0x50, 0);
/* DEVACTA */
pci_write_config_dword(pm_pcidev, 0x54, 0);
/* DEVACTB */
pci_write_config_dword(pm_pcidev, 0x58, 0);
/* DEVRESA */
pci_write_config_dword(pm_pcidev, 0x5c, 0);
/* DEVRESB */
pci_write_config_dword(pm_pcidev, 0x60, 0);
/* DEVRESC */
pci_write_config_dword(pm_pcidev, 0x64, 0); /* might kill the serial port */
/* DEVRESE */
pci_write_config_dword(pm_pcidev, 0x68, 0);
/* DEVRESF */
pci_write_config_dword(pm_pcidev, 0x6c, 0);
/* DEVRESG */
pci_write_config_dword(pm_pcidev, 0x70, 0);
/* DEVRESH */
pci_write_config_dword(pm_pcidev, 0x74, 0);
/* DEVRESI */
pci_write_config_dword(pm_pcidev, 0x78, 0);
/* DEVRESJ */
pci_write_config_dword(pm_pcidev, 0x7c, 0);
#endif
#if 1
/* Verify that smi is disabled */
printk_debug("Testing SMI\r\n");
{
u32 value;
pci_read_config_dword(pm_pcidev, 0x58, &value);
pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25));
}
outb(inb(0xb2), 0xb2);
printk_debug("SMI disabled\r\n");
#endif
#if 0
for(i = 0; i < 255; i++) {
printk_debug("%08x\r\n", i);
__rdtsc_delay2(1000000000UL, pm_io);
}
#endif
}

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# This will make a target directory of ./winfast
# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE
# CONFIG TOOL. Make it absolute if you like
target tsunami
mainboard tyan/s1846
# Enable Serial Console for debugging
# It will come up at 115200,8n1
option SERIAL_CONSOLE
# Enable MicroCode update and L2 Cache init for PII and PIII
option UPDATE_MICROCODE
option CONFIGURE_L2_CACHE
# Use the internal VGA frame buffer device
#option HAVE_FRAMEBUFFER
option USE_GENERIC_ROM
# Path to your kernel (vmlinux)
# NOTE; you need a path to your test12 kernel here.
linux /home/hcyun/Project/Linuxbios/linux
#linux /home/hcyun/Project/qpconf/proj1/build/linux/
# Kernel command line parameters
commandline root=/dev/hda1