From 4247128e39d06d31b4a298b9d23ad7a0f899b4f0 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 6 Jun 2025 11:55:21 -0500 Subject: [PATCH] soc/intel/cmn/block/aspm: Fix ASPM control for CPU root ports ASPM_AUTO is not a valid value for the CpuPcieRpAspm[x] UPD; setting it will result in the CPU root port having ASPM disabled by FSP. Fix this by modifying aspm_control_to_upd() to take into account whether it's being called for a PCH RP or a CPU RP, and setting the default value appropriately. TEST=build/boot starlabs/starfighter_rpl, verify CPU-attached RP and downstream attached device have ASPM L1 enabled. Change-Id: Ia89744fcae1294671061fb80be61b927a1578d4d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/87979 Reviewed-by: Sean Rhodes Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/aspm/aspm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c index afdf3f6fae..0a1196c569 100644 --- a/src/soc/intel/common/block/aspm/aspm.c +++ b/src/soc/intel/common/block/aspm/aspm.c @@ -40,15 +40,15 @@ * +-------------------+--------------------------+-----------+-----------+ */ -static unsigned int aspm_control_to_upd(enum ASPM_control aspm_control) +static unsigned int aspm_control_to_upd(enum ASPM_control aspm_control, bool is_cpu_rp) { /* Disable without Kconfig selected */ if (!CONFIG(PCIEXP_ASPM)) return UPD_INDEX(ASPM_DISABLE); - /* Use auto unless overwritten */ + /* Use default unless overwritten */ if (!aspm_control) - return UPD_INDEX(ASPM_AUTO); + return is_cpu_rp ? UPD_INDEX(ASPM_L0S_L1) : UPD_INDEX(ASPM_AUTO); return UPD_INDEX(aspm_control); } @@ -90,7 +90,7 @@ void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, s_cfg->PcieRpEnableCpm[index] = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); s_cfg->PcieRpAspm[index] = - aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), false); s_cfg->PcieRpL1Substates[index] = l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); s_cfg->PcieRpPcieSpeed[index] = @@ -120,7 +120,7 @@ void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; s_cfg->CpuPcieRpAspm[index] = - aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), true); s_cfg->CpuPcieRpL1Substates[index] = l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); }