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stddef: Add KHz, MHz and GHz constants

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This patch adds some simple constants to more easily write and do math
with frequencies, analogous to the existing KiB, MiB and GiB constants
for sizes. They are exemplary added to the Veyron_Pinky/Rk3288 code for
now and will hopefully be adopted by other parts of the codebase in the
future.

BUG=None
TEST=Compiled Veyron_Pinky.

Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221800
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Julius Werner 2014-10-06 13:41:28 -07:00 • committed by chrome-internal-fetch
commit 41bb802681
11 changed files with 45 additions and 42 deletions
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4
src/mainboard/google/veyron_pinky/bootblock.c
View file

@ -32,11 +32,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
setup_chromeos_gpios();
}

2
src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
View file

@ -69,7 +69,7 @@
.noc_timing = 0x2891E41D,
.noc_activate = 0x5B6,
.ddrconfig = 3,
.ddr_freq = 533000000,
.ddr_freq = 533*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,

2
src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
View file

@ -70,7 +70,7 @@
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666000000,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,

2
src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
View file

@ -70,7 +70,7 @@
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533000000,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,