From 41bb8026818b4381d4a6d43d2d433c207c3971bc Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 6 Oct 2014 13:41:28 -0700 Subject: [PATCH] stddef: Add KHz, MHz and GHz constants This patch adds some simple constants to more easily write and do math with frequencies, analogous to the existing KiB, MiB and GiB constants for sizes. They are exemplary added to the Veyron_Pinky/Rk3288 code for now and will hopefully be adopted by other parts of the codebase in the future. BUG=None TEST=Compiled Veyron_Pinky. Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/221800 Reviewed-by: David Hendricks --- src/include/stddef.h | 4 +++ src/mainboard/google/veyron_pinky/bootblock.c | 4 +-- .../sdram_inf/sdram-ddr3-hynix-2GB.inc | 2 +- .../sdram_inf/sdram-ddr3-samsung-2GB.inc | 2 +- .../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 2 +- src/soc/rockchip/rk3288/clock.c | 15 ++++----- src/soc/rockchip/rk3288/clock.h | 18 +++++------ src/soc/rockchip/rk3288/sdram.c | 32 +++++++++---------- src/soc/rockchip/rk3288/spi.c | 2 +- src/soc/rockchip/rk3288/timer.c | 1 - src/soc/rockchip/rk3288/timer.h | 5 +-- 11 files changed, 45 insertions(+), 42 deletions(-) diff --git a/src/include/stddef.h b/src/include/stddef.h index bd6c3babf3..43b287639e 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -26,6 +26,10 @@ typedef unsigned int wint_t; /* Could we ever run into this one? I hope we get this much memory! */ #define TiB (1<<40) +#define KHz (1000) +#define MHz (1000*KHz) +#define GHz (1000*MHz) + #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) #define check_member(structure, member, offset) _Static_assert( \ diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index d4f82decff..3ed8e273c7 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -32,11 +32,11 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc index 409a7cad35..07161c0dfa 100644 --- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ .noc_timing = 0x2891E41D, .noc_activate = 0x5B6, .ddrconfig = 3, - .ddr_freq = 533000000, + .ddr_freq = 533*MHz, .dramtype = DDR3, .num_channels = 2, .stride = 9, diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc index 3fdbecf6a8..f5793d1561 100644 --- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -70,7 +70,7 @@ .noc_timing = 0x30B25564, .noc_activate = 0x627, .ddrconfig = 3, - .ddr_freq = 666000000, + .ddr_freq = 666*MHz, .dramtype = DDR3, .num_channels = 2, .stride = 9, diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc index 315e542c39..f42f1b1b8b 100644 --- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -70,7 +70,7 @@ .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, .ddrconfig = 2, - .ddr_freq = 533000000, + .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, .stride = 9, diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 8202ef2127..0ce3f9450a 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -65,8 +65,8 @@ check_member(rk3288_cru_reg, cru_emmc_con[1], 0x021c); static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PLL_DIVISORS(hz, _nr, _no) {\ - .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / 24000000), .no = _no};\ - _Static_assert(((u64)hz * _nr * _no / 24000000) * 24000000 /\ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / (24*MHz)), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / (24*MHz)) * (24*MHz) /\ (_nr * _no) == hz,\ #hz "Hz cannot be hit with PLL divisors in " __FILE__); @@ -337,10 +337,10 @@ void rkclk_configure_ddr(unsigned int hz) { struct pll_div dpll_cfg; - if (hz <= 150000000) { + if (hz <= 150*MHz) { dpll_cfg.nr = 3; dpll_cfg.no = 8; - } else if (hz <= 540000000) { + } else if (hz <= 540*MHz) { dpll_cfg.nr = 6; dpll_cfg.no = 4; } else { @@ -348,10 +348,9 @@ void rkclk_configure_ddr(unsigned int hz) dpll_cfg.no = 1; } - dpll_cfg.nf = (hz / 1000 * dpll_cfg.nr * dpll_cfg.no) / 24000; - assert(dpll_cfg.nf < 4096 - && hz == dpll_cfg.nf * 24000 / (dpll_cfg.nr * dpll_cfg.no) - * 1000); + dpll_cfg.nf = (hz/KHz * dpll_cfg.nr * dpll_cfg.no) / (24*KHz); + assert(dpll_cfg.nf < 4096 && hz == dpll_cfg.nf * (24*KHz) / + (dpll_cfg.nr * dpll_cfg.no) * 1000); /* pll enter slow-mode */ writel(RK_CLRSETBITS(DPLL_MODE_MSK, DPLL_MODE_SLOW), &cru_ptr->cru_mode_con); diff --git a/src/soc/rockchip/rk3288/clock.h b/src/soc/rockchip/rk3288/clock.h index b206baa006..7a1dba0d85 100644 --- a/src/soc/rockchip/rk3288/clock.h +++ b/src/soc/rockchip/rk3288/clock.h @@ -22,17 +22,17 @@ #include "addressmap.h" -#define APLL_HZ 816000000 -#define GPLL_HZ 594000000 -#define CPLL_HZ 384000000 +#define APLL_HZ (816*MHz) +#define GPLL_HZ (594*MHz) +#define CPLL_HZ (384*MHz) -#define PD_BUS_ACLK_HZ 148500000 -#define PD_BUS_HCLK_HZ 148500000 -#define PD_BUS_PCLK_HZ 74250000 +#define PD_BUS_ACLK_HZ (148500*KHz) +#define PD_BUS_HCLK_HZ (148500*KHz) +#define PD_BUS_PCLK_HZ (74250*KHz) -#define PERI_ACLK_HZ 148500000 -#define PERI_HCLK_HZ 148500000 -#define PERI_PCLK_HZ 74250000 +#define PERI_ACLK_HZ (148500*KHz) +#define PERI_HCLK_HZ (148500*KHz) +#define PERI_PCLK_HZ (74250*KHz) void rkclk_init(void); void rkclk_configure_spi(unsigned int bus, unsigned int hz); diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 6c0c7fd136..2b0a396bb7 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -538,8 +538,8 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs, u32 freq) { int i; - if (freq <= 250000000) { - if (freq <= 150000000) + if (freq <= 250*MHz) { + if (freq <= 150*MHz) clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); else setbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); @@ -651,19 +651,19 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) writel(sdram_params->noc_activate, &msch_regs->activate); writel(BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1), &msch_regs->devtodev); - writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / 1000000 - * 5120, 1000)) - | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / 1000000 - * 50, 1000)) + writel(PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq/MHz + * 5120, 1000)) + | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq/MHz + * 50, 1000)) | PRT_ITMSRST(8), &ddr_publ_regs->ptr[0]); - writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq / 1000000 - * 500000, 1000)) - | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / 1000000 - * 400, 1000)), &ddr_publ_regs->ptr[1]); - writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq / 1000000 - * 200000, 1000)) - | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / 1000000 - * 1000, 1000)), &ddr_publ_regs->ptr[2]); + writel(PRT_DINIT0(div_round_up(sdram_params->ddr_freq/MHz + * 500000, 1000)) + | PRT_DINIT1(div_round_up(sdram_params->ddr_freq/MHz + * 400, 1000)), &ddr_publ_regs->ptr[1]); + writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq/MHz + * 200000, 1000)) + | PRT_DINIT3(div_round_up(sdram_params->ddr_freq/MHz + * 1000, 1000)), &ddr_publ_regs->ptr[2]); switch (sdram_params->dramtype) { case LPDDR3: @@ -971,9 +971,9 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) printk(BIOS_INFO, "Starting SDRAM initialization...\n"); if ((sdram_params->dramtype == DDR3 - && sdram_params->ddr_freq > 800000000) + && sdram_params->ddr_freq > 800*MHz) || (sdram_params->dramtype == LPDDR3 - && sdram_params->ddr_freq > 533000000)) + && sdram_params->ddr_freq > 533*MHz)) die("SDRAM frequency is to high!"); rkclk_configure_ddr(sdram_params->ddr_freq); diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 431b2d37f4..a74d423a62 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -36,7 +36,7 @@ struct rockchip_spi_slave { }; #define SPI_TIMEOUT_US 1000 -#define SPI_SRCCLK_HZ 99000000 +#define SPI_SRCCLK_HZ (99*MHz) #define SPI_FIFO_DEPTH 32 static struct rockchip_spi_slave rockchip_spi_slaves[3] = { diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index 2907ea1967..95f5be553c 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -18,7 +18,6 @@ */ #include -#include #include #include #include "timer.h" diff --git a/src/soc/rockchip/rk3288/timer.h b/src/soc/rockchip/rk3288/timer.h index 1820f56da4..9f1fbaf8c5 100644 --- a/src/soc/rockchip/rk3288/timer.h +++ b/src/soc/rockchip/rk3288/timer.h @@ -21,10 +21,11 @@ #define __SOC_ROCKCHIP_RK3288_TIMER_H__ #include +#include #include "addressmap.h" -#define SYS_CLK_FREQ 24000000 -static const u32 clocks_per_usec = SYS_CLK_FREQ/1000000; +#define SYS_CLK_FREQ (24*MHz) +static const u32 clocks_per_usec = SYS_CLK_FREQ/USECS_PER_SEC; struct rk3288_timer { u32 timer_load_count0;