mb/starlabs/*: Tidy up the devicetree files

Nit-pick tidy up, for things like indentation and using true/false for bools.

Change-Id: Icae88494306b48695e69fd878e11e648327b443d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2025-06-04 12:47:21 +01:00 committed by Matt DeVillier
commit 40c84c2577
6 changed files with 240 additions and 249 deletions

View file

@ -26,7 +26,6 @@ chip soc/intel/alderlake
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
# Device Tree
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
@ -187,9 +186,9 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "2"
register "add_acpi_dma_property" = "true"
register "skip_on_off_support" = "1"
register "skip_on_off_support" = "true"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
register "use_rp_mutex" = "true"
device generic 0 on end
end
end
@ -207,15 +206,16 @@ chip soc/intel/alderlake
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "1"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "is_storage" = "true"
register "add_acpi_dma_property" = "true"
register "skip_on_off_support" = "true"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
register "use_rp_mutex" = "true"
device generic 0 on end
end
end
@ -267,8 +267,8 @@ chip soc/intel/alderlake
subsystemid 0x1e50 0x7007
register "pch_hda_sdi_enable[0]" = "true"
register "pch_hda_dsp_enable" = "true"
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_audio_link_hda_enable" = "true"
register "pch_hda_idisp_codec_enable" = "true"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
end

View file

@ -24,7 +24,6 @@ chip soc/intel/meteorlake
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
# Device Tree
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
@ -188,6 +187,7 @@ chip soc/intel/meteorlake
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"M.2/M 2230"
@ -211,8 +211,8 @@ chip soc/intel/meteorlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"
"M.2/M 2280"

View file

@ -28,7 +28,6 @@ chip soc/intel/alderlake
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
# Device Tree
device domain 0 on
device ref igpu on
chip drivers/gfx/generic
@ -70,15 +69,16 @@ chip soc/intel/alderlake
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
register "srcclk_pin" = "4"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "is_storage" = "true"
register "add_acpi_dma_property" = "true"
register "skip_on_off_support" = "true"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
register "use_rp_mutex" = "true"
device generic 0 on end
end
end
@ -191,7 +191,6 @@ chip soc/intel/alderlake
end
end
end
end
device ref i2c0 on
chip drivers/i2c/hid
@ -215,6 +214,7 @@ chip soc/intel/alderlake
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"M.2/M 2230"
@ -223,10 +223,10 @@ chip soc/intel/alderlake
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "2"
register "skip_on_off_support" = "1"
register "add_acpi_dma_property" = "true"
register "skip_on_off_support" = "true"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
register "use_rp_mutex" = "true"
device generic 0 on end
end
end
@ -278,8 +278,8 @@ chip soc/intel/alderlake
subsystemid 0x1e50 0x7007
register "pch_hda_sdi_enable[0]" = "true"
register "pch_hda_dsp_enable" = "true"
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_audio_link_hda_enable" = "true"
register "pch_hda_idisp_codec_enable" = "true"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
end

View file

@ -1,22 +1,11 @@
chip soc/intel/tigerlake
# FSP UPDs
register "eist_enable" = "true"
register "enable_c6dram" = "1"
register "enable_c6dram" = "true"
register "CnviBtCore" = "true"
register "CnviBtAudioOffload" = "1"
register "CnviBtAudioOffload" = "true"
register "SaGv" = "SaGv_Enabled"
# Graphics
# Not used but timings left for reference
# register "panel_cfg" = "{
# .up_delay_ms = 2000, // T3
# .backlight_on_delay_ms = 0, // T7
# .backlight_off_delay_ms = 2000, // T9
# .down_delay_ms = 500, // T10
# .cycle_delay_ms = 500, // T12
# .backlight_pwm_hz = 200, // PWM
# }"
# Serial I/O
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@ -217,6 +206,7 @@ chip soc/intel/tigerlake
register "gen1_dec" = "0x00040069"
register "gen2_dec" = "0x00fc0201"
register "gen3_dec" = "0x000c0081"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end

View file

@ -76,11 +76,11 @@ chip soc/intel/alderlake
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
register "srcclk_pin" = "4"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "is_storage" = "true"
register "add_acpi_dma_property" = "true"
register "skip_on_off_support" = "true"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
register "use_rp_mutex" = "true"
device generic 0 on end
end
end
@ -230,9 +230,9 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "2"
register "add_acpi_dma_property" = "true"
register "skip_on_off_support" = "1"
register "skip_on_off_support" = "true"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
register "use_rp_mutex" = "true"
device generic 0 on end
end
end
@ -256,11 +256,11 @@ chip soc/intel/alderlake
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "1"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "is_storage" = "true"
register "add_acpi_dma_property" = "true"
register "skip_on_off_support" = "true"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
register "use_rp_mutex" = "true"
device generic 0 on end
end
end
@ -315,10 +315,10 @@ chip soc/intel/alderlake
end
device ref hda on
subsystemid 0x10ec 0x1200
register "pch_hda_sdi_enable[0]" = "1"
register "pch_hda_sdi_enable[0]" = "true"
register "pch_hda_dsp_enable" = "true"
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_audio_link_hda_enable" = "true"
register "pch_hda_idisp_codec_enable" = "true"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
end

View file

@ -187,15 +187,16 @@ chip soc/intel/alderlake
"SlotLengthLong"
"M.2/M 2242"
"SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "0"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "is_storage" = "true"
register "add_acpi_dma_property" = "true"
register "skip_on_off_support" = "true"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
register "use_rp_mutex" = "true"
device generic 0 on end
end
end
@ -248,8 +249,8 @@ chip soc/intel/alderlake
subsystemid 0x1e50 0x7038
register "pch_hda_sdi_enable[0]" = "true"
register "pch_hda_dsp_enable" = "true"
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_audio_link_hda_enable" = "true"
register "pch_hda_idisp_codec_enable" = "true"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
end