From 3fe4b00966e0eadd56c627bfa70fb846d66eb731 Mon Sep 17 00:00:00 2001 From: John Su Date: Mon, 5 May 2025 15:21:32 +0800 Subject: [PATCH] mb/trulo/var/uldrenite: Swap ISH UART from UART1 to UART0 As per the requirement, the ISH UART needs to be the same as Trulo, so swap ISH UART from UART1 to UART0. And configure ISH_UART0 GPIO; if not used, the pins will be set to NC. Additionally, the LCD_CBL_DET# pin has been changed from GPP_D14 to GPP_D18. BUG=b:415605630, b:411249861 TEST=emerge-nissa coreboot Change-Id: I88bca9a56fa96ad0a52c29fec12b8d4dbee23be4 Signed-off-by: John Su Reviewed-on: https://review.coreboot.org/c/coreboot/+/87535 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Dtrain Hsu --- .../google/brya/variants/uldrenite/gpio.c | 16 ++++++++-------- .../google/brya/variants/uldrenite/variant.c | 4 ++++ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c index d453adb181..667a369604 100644 --- a/src/mainboard/google/brya/variants/uldrenite/gpio.c +++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c @@ -143,18 +143,18 @@ static const struct pad_config gpio_table[] = { PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG), /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), - /* D13 : UART0_ISH_RXD ==> NC */ - PAD_NC(GPP_D13, NONE), - /* D14 : UART0_ISH_TXD ==> LCD_CBL_DET# */ - PAD_CFG_GPO(GPP_D14, 1, DEEP), + /* D13 : UART0_ISH_RXD */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : UART0_ISH_TXD */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */ PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> SOC_TS_I2C_INT# */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), - /* D17 : NC ==> UART1_ISH_RX_DBG_TX */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), - /* D18 : NC ==> UART1_ISH_TX_DBG_RX */ - PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2), + /* D17 : NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : LCD_CBL_DET# */ + PAD_CFG_GPO(GPP_D18, 1, DEEP), /* D19 : I2S_MCLK1_OUT ==> NC */ PAD_NC(GPP_D19, NONE), diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c index f5d01c1a89..a2ed02247d 100644 --- a/src/mainboard/google/brya/variants/uldrenite/variant.c +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -50,6 +50,10 @@ static const struct pad_config ish_disable_pads[] = { PAD_NC(GPP_B6, NONE), /* D1 : ISH_GP1 ==> NC */ PAD_NC(GPP_D1, NONE), + /* D13 : UART0_ISH_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : UART0_ISH_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), /* E9 : SOC_ACC2_INT ==> NC */ PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), };