From 3f3ea8bb58f8fc65148047b9d2f3274589a6636a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 11 Nov 2024 18:36:27 +0530 Subject: [PATCH] soc/intel/pantherlake: Add config option to limit DRAM frequency This patch adds a new config option to limit the maximum DRAM frequency for Pantherlake platforms. The mainboard code should try to set `max_dram_speed_mts` from override device tree if required. BUG=b:373394046 TEST=Able to build and boot google/fatcat. Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/85101 Reviewed-by: Amanda Hwang Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/soc/intel/pantherlake/chip.h | 2 ++ src/soc/intel/pantherlake/romstage/fsp_params.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index b59ce5e8e6..5846037c95 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -512,6 +512,8 @@ struct soc_intel_pantherlake_config { */ uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; + uint16_t max_dram_speed_mts; + }; typedef struct soc_intel_pantherlake_config config_t; diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index b105d3d58a..e6ed19ec85 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -74,6 +74,9 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; } + if (config->max_dram_speed_mts) + m_cfg->DdrFreqLimit = config->max_dram_speed_mts; + m_cfg->RMT = config->rmt; m_cfg->MrcFastBoot = 1; }