diff --git a/src/northbridge/intel/broadwell/Makefile.mk b/src/northbridge/intel/broadwell/Makefile.mk
index 16576371ae..e067285881 100644
--- a/src/northbridge/intel/broadwell/Makefile.mk
+++ b/src/northbridge/intel/broadwell/Makefile.mk
@@ -2,7 +2,7 @@
 
 ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y)
 
-bootblock-y += bootblock.c
+bootblock-y += ../haswell/bootblock.c
 
 romstage-y += early_init.c
 romstage-y += raminit.c
diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c
deleted file mode 100644
index 8c851cac5d..0000000000
--- a/src/northbridge/intel/broadwell/bootblock.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/bootblock.h>
-#include <assert.h>
-#include <device/pci_ops.h>
-#include <soc/pci_devs.h>
-#include <soc/systemagent.h>
-
-static uint32_t encode_pciexbar_length(void)
-{
-	switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
-		case 256: return 0 << 1;
-		case 128: return 1 << 1;
-		case  64: return 2 << 1;
-		default:  return dead_code_t(uint32_t);
-	}
-}
-
-void bootblock_early_northbridge_init(void)
-{
-	/*
-	 * The "io" variant of the config access is explicitly used to setup the
-	 * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
-	 * subsequent non-explicit config accesses use MCFG. This code also assumes
-	 * that bootblock_northbridge_init() is the first thing called in the non-asm
-	 * boot block code. The final assumption is that no assembly code is using the
-	 * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
-	 *
-	 * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
-	 */
-	const uint32_t reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
-}