From 3bd554feb2be49e7af82a8932a8ca4ad3c521764 Mon Sep 17 00:00:00 2001 From: Crystal Guo Date: Fri, 28 Nov 2025 10:40:44 +0800 Subject: [PATCH] soc/mediatek/mt8196: Align the struct for storing DRAM calibration data The current read calibration data flow may cause memory overwrite due to struct size mismatch, resulting in fast calibration flow failure. Need to align the struct for storing DRAM calibration data between coreboot and mtk-dramk repo to prevent memory overwrite. BUG=b:450724525 TEST=Bootup ok. Change-Id: Ic59bc9c7f12c454702ba894dea5dce94984e2121 Signed-off-by: Crystal Guo Reviewed-on: https://review.coreboot.org/c/coreboot/+/90354 Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin Reviewed-by: jason-ch chen Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8196/include/soc/dramc_param.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_param.h b/src/soc/mediatek/mt8196/include/soc/dramc_param.h index 819b1af6ce..7902336bc0 100644 --- a/src/soc/mediatek/mt8196/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8196/include/soc/dramc_param.h @@ -13,7 +13,7 @@ #include #include -#define DRAMC_PARAM_HEADER_VERSION 4 +#define DRAMC_PARAM_HEADER_VERSION 5 struct sdram_params { /* rank, cbt */ @@ -21,7 +21,7 @@ struct sdram_params { u32 dram_cbt_mode; u16 delay_cell_timex100; - u8 u18ph_dly; + u8 u18ph_dly[CHANNEL_MAX]; /* duty */ s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; @@ -91,7 +91,7 @@ struct sdram_params { /* tx oe */ u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; - u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX]; + u16 tx_oe_offset[DQS_NUMBER_LP5]; }; struct dramc_data {