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vendorcode/intel/fsp/skx_sp: Fix PCI domain scanning

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Properly scan all logical stack when creating PCI domains.
Fixes PCI bus ranges being used on other stacks, since they look
unused, as not all stacks are checked.

Change-Id: I13c8b389a585dbccec182d3c98021f1d9d648b2c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Patrick Rudolph 2024-11-14 13:57:16 +01:00 • committed by Lean Sheng Tan
commit 3a7102d628
1 changed files with 1 additions and 3 deletions
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4
src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
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@ -137,9 +137,7 @@ typedef enum {
} IIO_STACKS;
#define IioStack0 CSTACK
/* MAX_LOGIC_IIO_STACK is needed by uncore_acpi.c, define the same value from nb_acpi.c for
Skylake-SP to keep the same behavior. */
#define MAX_LOGIC_IIO_STACK PSTACK2
#define MAX_LOGIC_IIO_STACK MAX_STACKS
/**
NTB Per Port Definition