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mb/ocp/tiogapass: Fix GPIOs

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Do not enable SMIs on GPIOs since there's no SMI handler.

Without an SMI handler this will just slow down the platform once
the SMI asserts since it's never cleared. Once the protocol between
BMC and x86 has been implemented in an SMI handler, this can be reverted.

TEST: Booted on OCP/tiogapass without massive slowdown when SMIs are enabled.

Change-Id: If16c2c427f9b160f78a768a01a60128a6ed2c53f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
This commit is contained in:
Patrick Rudolph 2024-11-14 11:53:43 +01:00 • committed by Lean Sheng Tan
commit 00b0285b36
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h
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@ -197,13 +197,13 @@ static const struct pad_config gpio_table[] = {
/* GPP_C21 - GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, DEEP, OFF, DRIVER),
/* GPP_C22 - GPIO */
PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, LEVEL, NONE),
PAD_CFG_GPI(GPP_C22, NONE, PLTRST),
/* GPP_C23 - GPIO */
PAD_CFG_GPI_SMI(GPP_C23, NONE, DEEP, LEVEL, INVERT),
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
/* ------- GPIO Group GPP_D ------- */
/* GPP_D0 - GPIO */
PAD_CFG_GPI_SMI(GPP_D0, NONE, PLTRST, LEVEL, INVERT),
PAD_CFG_GPI(GPP_D0, NONE, PLTRST),
/* GPP_D1 - GPIO */
PAD_CFG_GPO(GPP_D1, 0, DEEP),
/* GPP_D2 - GPIO */
@ -253,9 +253,9 @@ static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPP_E ------- */
/* GPP_E0 - GPIO */
PAD_CFG_GPI_SMI(GPP_E0, NONE, DEEP, LEVEL, NONE),
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
/* GPP_E1 - GPIO */
PAD_CFG_GPI_SMI(GPP_E1, NONE, DEEP, LEVEL, NONE),
PAD_CFG_GPI(GPP_E1, NONE, DEEP),
/* GPP_E2 - GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER),
/* GPP_E3 - CPU_GP0 */