erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: ramstage: Align stack to 16 bytes

Browse source 
Some SSE instructions could take 128bit memory operands from
stack.

AGESA vendorcode was always built with SSE enabled, but until
now stack alignment was not known to cause major issues. Seems
like GCC-6.3 more likely emits instructions that depend on the
16 byte alignment of stack.

BUG=none
BRANCH=none
TEST=none

Change-Id: I58ae02a2204f426b89f892a0421f916711bd91f0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4796c32ad6
Original-Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18823
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457365
This commit is contained in:
Kyösti Mälkki 2017-03-15 08:07:22 +02:00 • committed by chrome-bot
commit 3754c09cc7
1 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/arch/x86/c_start.S
View file

@ -110,6 +110,8 @@ _start:
*/
post_code(POST_PRE_HARDWAREMAIN) /* post fe */
andl $0xFFFFFFF0, %esp
#if CONFIG_GDB_WAIT
call gdb_hw_init
call gdb_stub_breakpoint