From 3754c09cc72e1c4f65806084f343c4522bb36ef1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 15 Mar 2017 08:07:22 +0200 Subject: [PATCH] UPSTREAM: ramstage: Align stack to 16 bytes Some SSE instructions could take 128bit memory operands from stack. AGESA vendorcode was always built with SSE enabled, but until now stack alignment was not known to cause major issues. Seems like GCC-6.3 more likely emits instructions that depend on the 16 byte alignment of stack. BUG=none BRANCH=none TEST=none Change-Id: I58ae02a2204f426b89f892a0421f916711bd91f0 Signed-off-by: Patrick Georgi Original-Commit-Id: 4796c32ad60933bd8c23729684414121097b0445 Original-Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c Original-Signed-off-by: Kysti Mlkki Original-Reviewed-on: https://review.coreboot.org/18823 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel Original-Reviewed-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/457365 --- src/arch/x86/c_start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 29d3a538b4..9ad2698483 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -110,6 +110,8 @@ _start: */ post_code(POST_PRE_HARDWAREMAIN) /* post fe */ + andl $0xFFFFFFF0, %esp + #if CONFIG_GDB_WAIT call gdb_hw_init call gdb_stub_breakpoint