diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index 9c454e6f7f..bd84488762 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -35,6 +35,13 @@ config BOARD_LENOVO_T480S
 	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 	select VARIANT_HAS_DGPU
 
+config BOARD_LENOVO_T580
+	bool
+	select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+	select MEC1653_HAS_DEBUG_UNLOCK
+	select VARIANT_HAS_DGPU
+
+
 if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
 
 config MAINBOARD_DIR
@@ -43,6 +50,7 @@ config MAINBOARD_DIR
 config VARIANT_DIR
 	default "t480" if BOARD_LENOVO_T480
 	default "t480s" if BOARD_LENOVO_T480S
+	default "t580" if BOARD_LENOVO_T580
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -50,6 +58,7 @@ config OVERRIDE_DEVICETREE
 config MAINBOARD_PART_NUMBER
 	default "T480" if BOARD_LENOVO_T480
 	default "T480s" if BOARD_LENOVO_T480S
+	default "T580" if BOARD_LENOVO_T580
 
 config CBFS_SIZE
 	default 0x900000
@@ -85,7 +94,7 @@ config THINKPADEC_HKEY_EISAID
 	default "LEN0268"
 
 config MEC1653_DEBUG_UNLOCK_KEY
-	default "7a41b149fe2101cf" if BOARD_LENOVO_T480
+	default "7a41b149fe2101cf" if BOARD_LENOVO_T480 || BOARD_LENOVO_T580
 
 config VARIANT_HAS_DGPU
 	bool
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
index abc273f387..21b9739e6f 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
@@ -5,3 +5,6 @@ config BOARD_LENOVO_T480
 
 config BOARD_LENOVO_T480S
 	bool "ThinkPad T480s"
+
+config BOARD_LENOVO_T580
+	bool "ThinkPad T580"
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/data.vbt
new file mode 100644
index 0000000000..79b206a214
Binary files /dev/null and b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/data.vbt differ
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      DP1,
+      DP2,
+      HDMI1,
+      HDMI2,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c
new file mode 100644
index 0000000000..9c0da3c37e
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../variant.h"
+
+/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style
+ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */
+
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),				/* -KBRC */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),				/* LPC_AD0 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),				/* LPC_AD1 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),				/* LPC_AD2 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),				/* LPC_AD3 */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),				/* -LPC_FRAME */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),				/* IRQSER */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),				/* -TPM_IRQ */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),				/* -CLKRUN */
+	PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1),				/* LPCCLK_EC_24M */
+	PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1),				/* LPCCLK_DEBUG_24M */
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1),				/* -SUSWARN */
+	PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1),				/* -SUS_STAT */
+	PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1),				/* -SUSWARN */
+	PAD_NC(GPP_A16, NONE),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, NONE),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_NC(GPP_B0, NONE),
+	PAD_NC(GPP_B1, NONE),
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),				/* -CLKREQ_PCIE0 */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),				/* -CLKREQ_PCIE4 */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),				/* -CLKREQ_PCIE5 */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),				/* -CLKREQ_PCIE10 */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),				/* -CLKREQ_PCIE8 */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),				/* -CLKREQ_PCIE6 */
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),				/* -PCH_SLP_S0 */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),				/* -PLTRST */
+	PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1),				/* PCH_SPKR */
+	PAD_CFG_GPO(GPP_B15, 1, DEEP),					/* NFC_DLREQ */
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),				/* SMB_CLK */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),				/* SMB_DATA */
+	PAD_NC(GPP_C2, NONE),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),				/* SML0_CLK */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),				/* SML0_DATA */
+	PAD_NC(GPP_C5, NONE),
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),				/* EC_SCL2 */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),				/* EC_SDA2 */
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),				/* I2C0_DATA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),				/* I2C0_CLK */
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
+	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
+	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
+	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_NC(GPP_D5, NONE),
+	PAD_NC(GPP_D6, NONE),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI),		/* -DISCRETE_PRESENCE */
+	PAD_NC(GPP_D10, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI),		/* DGFX_VRAM_ID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI),		/* DGFX_VRAM_ID1 */
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),					/* DDI_PRIORITY1 */
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI),		/* -NFC_DTCT */
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),				/* -WWAN_SATA_DTCT (always HIGH) */
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),				/* -PE_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI),	/* -TBT_PLUG_EVENT */
+	PAD_CFG_GPO(GPP_E4, 1, DEEP),					/* NFC_ON */
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1),				/* SATA2_DEVSLP */
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E8, NONE),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),				/* -USB_PORT0_OC0 (AON port) */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),				/* -USB_PORT1_OC1 (regular port) */
+	PAD_NC(GPP_E11, NONE),
+	PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP),			/* NFC_INT */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),				/* DDIP1_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),				/* DDIP2_HPD */
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),				/* EDP_HPD */
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),				/* DDIP2_CTRLCLK */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),				/* DDIP2_CTRLDATA */
+	PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST),			/* -GPU_RST */
+	PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST),			/* 1R8VIDEO_AON_ON */
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),				/* -BATLOW */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),				/* AC_PRESENT */
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),				/* -LANWAKE */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),				/* -PWRSW_EC */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),				/* -PCH_SLP_S3 */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),				/* -PCH_SLP_S4 */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),				/* -PCH_SLP_M */
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),				/* SUSCLK_32K */
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),				/* -PCH_SLP_WLAN */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),				/* -PCH_SLP_S5 */
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),				/* LANPHYPC */
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI),		/* GC6_FB_EN */
+	PAD_CFG_GPO(GPP_F2, 1, DEEP),					/* -GPU_EVENT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI),		/* DGFX_PWRGD */
+	PAD_CFG_GPO(GPP_F4, 1, DEEP),					/* -WWAN_RESET */
+	PAD_NC(GPP_F5, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI),		/* -MIC_HW_EN (R961 to GND) */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI),		/* -INT_MIC_DTCT */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI),		/* WWAN_CFG3 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI),		/* PLANARID0 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI),		/* PLANARID1 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI),		/* PLANARID2 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI),		/* PLANARID3 */
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_NC(GPP_F20, NONE),
+	PAD_NC(GPP_F21, NONE),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI),		/* -INTRUDER_PCH */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI),		/* -SC_DTCT */
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, NONE),
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
+	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
+	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
+	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
+};
+
+void variant_config_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c
new file mode 100644
index 0000000000..65245c8e21
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/hda_verb.c
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0257, // Vendor/Device ID: Realtek ALC257
+	0x17aa225a, // Subsystem ID
+	11,
+	AZALIA_SUBVENDOR(0, 0x17aa225a),
+
+	AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_MIC_IN,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		2, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+		AZALIA_INTEGRATED,
+		AZALIA_INTERNAL,
+		AZALIA_SPEAKER,
+		AZALIA_OTHER_ANALOG,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_NO_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_MIC_IN,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		3, 0
+	)),
+	AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
+	AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+		AZALIA_HP_OUT,
+		AZALIA_STEREO_MONO_1_8,
+		AZALIA_BLACK,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 15
+	)),
+
+	0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
+	0x80860101, // Subsystem ID
+	4,
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+	AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+		AZALIA_JACK,
+		AZALIA_DIGITAL_DISPLAY,
+		AZALIA_DIGITAL_OTHER_OUT,
+		AZALIA_OTHER_DIGITAL,
+		AZALIA_COLOR_UNKNOWN,
+		AZALIA_JACK_PRESENCE_DETECT,
+		1, 0
+	)),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/include/variant/dgpu.h b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/include/variant/dgpu.h
new file mode 100644
index 0000000000..deb0cf4c1e
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/include/variant/dgpu.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VARIANT_DGPU_H_
+#define _VARIANT_DGPU_H_
+
+#define GPIO_GPU_RST			GPP_E22 // active low
+#define GPIO_1R8VIDEO_AON_ON		GPP_E23
+
+#define GPIO_DGFX_PWRGD			GPP_F3
+
+#define GPIO_DISCRETE_PRESENCE		GPP_D9	// active low
+#define GPIO_DGFX_VRAM_ID0		GPP_D11
+#define GPIO_DGFX_VRAM_ID1		GPP_D12
+
+#endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/memory_init_params.c
new file mode 100644
index 0000000000..926cdf021a
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/memory_init_params.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	mem_cfg->DqPinsInterleaved = false;			/* DDR_DQ in interleave mode */
+	mem_cfg->CaVrefConfig      = 2;				/* VREF_CA to CH_A and VREF_DQ_B to CH_B */
+	mem_cfg->MemorySpdDataLen  = CONFIG_DIMM_SPD_SIZE;
+
+	/* Get SPD for memory slots */
+	struct spd_block blk = { .addr_map = { 0x50, 0x51, } };
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+
+	mem_cfg->MemorySpdPtr00    = (uintptr_t)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10    = (uintptr_t)blk.spd_array[1];
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/overridetree.cb
new file mode 100644
index 0000000000..34320187ad
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/overridetree.cb
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC1),		// USB-A
+				[1] = USB2_PORT_MID(OC0),		// USB-A (always on)
+				[2] = USB2_PORT_MID(OC_SKIP),		// JSC-1 (smartcard slot)
+				[3] = USB2_PORT_MID(OC_SKIP),		// USB-C (charging port)
+				[4] = USB2_PORT_MID(OC_SKIP),		// JCAM1 (IR camera)
+				[5] = USB2_PORT_MID(OC_SKIP),		// JWWAN1 (M.2 WWAN USB)
+				[6] = USB2_PORT_MID(OC_SKIP),		// JWLAN1 (M.2 WLAN USB)
+				[7] = USB2_PORT_MID(OC_SKIP),		// JCAM1 (webcam)
+				[8] = USB2_PORT_MID(OC_SKIP),		// JFPR1 (fingerprint reader)
+				[9] = USB2_PORT_MID(OC_SKIP),		// JLCD1 (touch panel)
+			}"
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC1),		// USB-A
+				[1] = USB3_PORT_DEFAULT(OC0),		// USB-A (always on)
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	// RTS5344S (SD card reader)
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	// USB-C (charging port)
+			}"
+		end
+
+		# PCIe controller 1 - 1x4
+		#   PCIE 1-4   - RP1  - dGPU - CLKOUT0 - CLKREQ0
+		#
+		# PCIe controller 2 - 2x1+1x2 (lane reversal)
+		#   PCIE 5     - GBE  - GBE  - CLKOUT1 - CLKREQ1 (clobbers RP8)
+		#   PCIE 6     - RP7  - WLAN - CLKOUT2 - CLKREQ2
+		#   PCIE 7-8   - RP5  - WWAN - CLKOUT3 - CLKREQ3
+		#
+		# PCIe controller 3 - 2x2
+		#   PCIE 9-10  - RP9  - TB3  - CLKOUT4 - CLKREQ4
+		#   PCIE 11-12 - RP11 - SSD  - CLKOUT5 - CLKREQ5
+
+		# dGPU - x4
+		device ref pcie_rp1 on
+			register "PcieRpClkReqSupport[0]"		= "true"
+			register "PcieRpClkReqNumber[0]"		= "0"
+			register "PcieRpClkSrcNumber[0]"		= "0"
+			register "PcieRpAdvancedErrorReporting[0]"	= "true"
+			register "PcieRpLtrEnable[0]"			= "true"
+			device generic 0 alias dgpu on end
+		end
+
+		# Ethernet (clobbers RP8)
+		device ref gbe on
+			register "LanClkReqSupported"			= "true"
+			register "LanClkReqNumber"			= "1"
+			register "EnableLanLtr"				= "true"
+			register "EnableLanK1Off"			= "true"
+		end
+
+		# M.2 WLAN - x1
+		device ref pcie_rp7 on
+			register "PcieRpClkReqSupport[6]"		= "true"
+			register "PcieRpClkReqNumber[6]"		= "2"
+			register "PcieRpClkSrcNumber[6]"		= "2"
+			register "PcieRpAdvancedErrorReporting[6]"	= "true"
+			register "PcieRpLtrEnable[6]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
+		end
+
+		# M.2 WWAN - x2
+		device ref pcie_rp5 on
+			register "PcieRpClkReqSupport[4]"		= "true"
+			register "PcieRpClkReqNumber[4]"		= "5"
+			register "PcieRpClkSrcNumber[4]"		= "5"
+			register "PcieRpAdvancedErrorReporting[4]"	= "true"
+			register "PcieRpLtrEnable[4]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket2" "SlotLengthOther" "M.2/B 3042/2242" "SlotDataBusWidth2X"
+		end
+
+		# TB3 (Alpine Ridge LP) - x2
+		device ref pcie_rp9 on
+			register "PcieRpClkReqSupport[8]"		= "true"
+			register "PcieRpClkReqNumber[8]"		= "4"
+			register "PcieRpClkSrcNumber[8]"		= "4"
+			register "PcieRpAdvancedErrorReporting[8]"	= "true"
+			register "PcieRpLtrEnable[8]"			= "true"
+			register "PcieRpHotPlug[8]"			= "true"
+		end
+
+		# M.2 2280 caddy - x2
+		device ref pcie_rp11 on
+			register "PcieRpClkReqSupport[10]"		= "true"
+			register "PcieRpClkReqNumber[10]"		= "3"
+			register "PcieRpClkSrcNumber[10]"		= "3"
+			register "PcieRpAdvancedErrorReporting[10]"	= "true"
+			register "PcieRpLtrEnable[10]"			= "true"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 Sub Card" "SlotDataBusWidth2X"
+		end
+	end
+end