From 33fdda93c02204a4e7abc05093bc2dabdc11af4c Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Fri, 11 Oct 2024 11:49:03 +0100 Subject: [PATCH] mb/starlabs/*: Set ASPM and L1SS in devicetree Explicitly set ASPM and L1 Substates to maximum, to avoid instances where the default "AUTO" in FSP will fail to detect the highest level. Tested on all devices, with Ubuntu 24.04 by verifying general functionality of the connected device. Change-Id: I9f156124925bebd8588d863661bb2702c552f657 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/84727 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- .../starlabs/byte_adl/variants/mk_ii/devicetree.cb | 6 ++++++ src/mainboard/starlabs/starbook/variants/adl/devicetree.cb | 4 ++++ src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb | 4 ++++ .../starlabs/starfighter/variants/rpl/devicetree.cb | 4 ++++ .../starlabs/starlite_adl/variants/mk_v/devicetree.cb | 2 ++ 5 files changed, 20 insertions(+) diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index f514a35d6d..e66c106e0e 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -141,6 +141,8 @@ chip soc/intel/alderlake .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen4x1" @@ -153,6 +155,8 @@ chip soc/intel/alderlake .clk_src = 3, .clk_req = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" @@ -164,6 +168,8 @@ chip soc/intel/alderlake .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index a17b7ece17..c074a61b52 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -143,6 +143,8 @@ chip soc/intel/alderlake .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" @@ -160,6 +162,8 @@ chip soc/intel/alderlake .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_detect_timeout_ms = 50, }" diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index a411446638..b1cb70b812 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -35,6 +35,8 @@ chip soc/intel/alderlake .clk_src = 4, .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypeM2Socket3" @@ -173,6 +175,8 @@ chip soc/intel/alderlake .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index f6551bf221..18c58fec33 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -41,6 +41,8 @@ chip soc/intel/alderlake .clk_src = 4, .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypeM2Socket3" @@ -186,6 +188,8 @@ chip soc/intel/alderlake .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 02f96f6c8f..c2a3553ed8 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -149,6 +149,8 @@ chip soc/intel/alderlake .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypeM2Socket3"