kirby: Update kirby and get it to build again.
Update the kirby mainboard files so they build again and are current with pit. BUG=chrome-os-partner:19420 TEST=Built for kirby. BRANCH=None Change-Id: Ie6d9fcd4e620d2d82b4b2083b713d64e6e72d55e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65936 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black
ChromeBot
parent
7e7befdc39
commit
2f2c9ce2ad
2 changed files with 128 additions and 29 deletions
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@ -17,6 +17,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <string.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/i2c.h>
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@ -34,6 +35,7 @@
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#include <cpu/samsung/exynos5420/power.h>
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#include <cpu/samsung/exynos5420/i2c.h>
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#include <cpu/samsung/exynos5420/dp.h>
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#include <cpu/samsung/exynos5420/fimd.h>
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#include <drivers/parade/ps8625/ps8625.h>
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#include <ec/google/chromeec/ec.h>
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#include <stdlib.h>
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@ -52,6 +54,64 @@ static struct edid edid = {
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.bytes_per_line = 2 * 1366
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};
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/* from the fdt */
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static struct vidinfo vidinfo = {
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.vl_freq = 60,
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.vl_col = 1366,
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.vl_row = 768,
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.vl_width = 1366,
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.vl_height = 768,
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.vl_clkp = 1,
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.vl_dp = 1,
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.vl_bpix = 4,
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.vl_hspw = 32,
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.vl_hbpd = 40,
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.vl_hfpd = 40,
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.vl_vspw = 6,
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.vl_vbpd = 10,
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.vl_vfpd = 12,
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.vl_cmd_allow_len = 0xf,
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.win_id = 3,
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.dp_enabled = 1,
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.dual_lcd_enabled = 0,
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.interface_mode = FIMD_RGB_INTERFACE,
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};
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static unsigned char panel_edid[] = {
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0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
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0x06,0xaf,0x5c,0x31,0x00,0x00,0x00,0x00,
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0x00,0x16,0x01,0x03,0x80,0x1a,0x0e,0x78,
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0x0a,0x99,0x85,0x95,0x55,0x56,0x92,0x28,
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0x22,0x50,0x54,0x00,0x00,0x00,0x01,0x01,
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0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
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0x01,0x01,0x01,0x01,0x01,0x01,0xa3,0x1b,
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0x56,0x7e,0x50,0x00,0x16,0x30,0x30,0x20,
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0x36,0x00,0x00,0x90,0x10,0x00,0x00,0x18,
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0x6d,0x12,0x56,0x7e,0x50,0x00,0x16,0x30,
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0x30,0x20,0x36,0x00,0x00,0x90,0x10,0x00,
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0x00,0x18,0x00,0x00,0x00,0xfe,0x00,0x41,
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0x55,0x4f,0x0a,0x20,0x20,0x20,0x20,0x20,
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0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xfe,
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0x00,0x42,0x31,0x31,0x36,0x58,0x57,0x30,
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0x33,0x20,0x56,0x31,0x20,0x0a,0x00,0x3d,
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0x00,0xc0,0x00,0x00,0x27,0xfd,0x00,0x20,
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0x02,0x59,0x07,0x00,0x64,0x3e,0x07,0x02,
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0x00,0x00,0xcd,0x12,0x59,0xff,0x10,0x03,
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0x00,0x00,0x00,0x00,0x64,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x05,0x00,0x00,0x00,
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0x9c,0x3f,0x07,0x02,0x31,0xf9,0x00,0x20,
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0x59,0xff,0x10,0x03,0x00,0x00,0x00,0x00,
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0xbc,0x3e,0x07,0x02,0xc0,0x9b,0x01,0x20,
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0x00,0x00,0x00,0x00,0xdb,0xf8,0x00,0x20,
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0x98,0x3e,0x07,0x02,0x8b,0xaf,0x00,0x20,
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0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0xe5,0xcd,0x16,0x00,0xe9,0xcd,0x16,0x00,
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0xe8,0x03,0x00,0x00,0x6c,0x55,0x01,0x20,
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0x2c,0x01,0x00,0x00,0x85,0xbb,0x00,0x20,
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0xe8,0x03,0x00,0x00,0xe9,0xcd,0x16,0x00,
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};
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static const struct parade_write parade_writes[] = {
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{ 0x02, 0xa1, 0x01 }, /* HPD low */
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/*
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@ -175,6 +235,8 @@ static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */
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static void parade_dp_bridge_setup(void)
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{
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int i;
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gpio_set_value(dp_pd_l, 1);
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gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT);
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gpio_set_pull(dp_pd_l, GPIO_PULL_NONE);
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@ -185,6 +247,8 @@ static void parade_dp_bridge_setup(void)
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udelay(10);
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gpio_set_value(dp_rst_l, 1);
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gpio_set_pull(dp_hpd, GPIO_PULL_NONE);
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gpio_cfg_pin(dp_hpd, GPIO_INPUT);
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/* De-assert PD (and possibly RST) to power up the bridge. */
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@ -198,9 +262,19 @@ static void parade_dp_bridge_setup(void)
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exynos_pinmux_i2c7();
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i2c_init(7, 100000, 0x00);
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parade_ps8625_bridge_setup(7, 0x48,
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parade_writes,
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parade_ps8625_bridge_setup(7, 0x48, parade_writes,
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ARRAY_SIZE(parade_writes));
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/* Spin until the display is ready.
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* It's quite important to try really hard to get the display up,
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* so be generous. It will typically be ready in only 5 ms. and
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* we're out of here.
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* If it's not ready after a second, then we're in big trouble.
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*/
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for(i = 0; i < 1000; i++){
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if (gpio_get_value(dp_hpd))
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break;
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mdelay(1);
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}
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}
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/*
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@ -223,22 +297,17 @@ static void backlight_pwm(void)
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udelay(LCD_T6_DELAY_MS * 1000);
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}
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//static struct video_info smdk5420_dp_config = {
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static struct video_info dp_video_info = {
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/* FIXME: fix video_info struct to use const for name */
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.name = (char *)"eDP-LVDS NXP PTN3460",
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static struct edp_video_info dp_video_info = {
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.master_mode = 0,
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.h_sync_polarity = 0,
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.v_sync_polarity = 0,
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.interlaced = 0,
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.color_space = COLOR_RGB,
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.dynamic_range = VESA,
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.ycbcr_coeff = COLOR_YCBCR601,
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.color_depth = COLOR_8,
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.link_rate = LINK_RATE_2_70GBPS,
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.lane_count = LANE_COUNT2,
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};
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/* FIXME: move some place more appropriate */
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@ -277,14 +346,13 @@ static void backlight_vdd(void)
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/* this happens after cpu_init where exynos resources are set */
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static void mainboard_init(device_t dev)
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{
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struct s5p_dp_device dp_device = {
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.base = (struct exynos5_dp *)EXYNOS5420_DP1_BASE,
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.video_info = &dp_video_info,
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};
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/* we'll stick with the crummy u-boot struct for now.*/
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/* doing this as an auto since the struct has to be writeable */
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struct edp_device_info device_info;
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void *fb_addr = (void *)(get_fb_base_kb() * KiB);
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gpio_init();
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tmu_init(&exynos5420_tmu_info);
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/* Clock Gating all the unused IP's to save power */
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@ -295,18 +363,40 @@ static void mainboard_init(device_t dev)
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set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
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/*
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* The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000
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* should be 0 according to the datasheet, but has experimentally
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* been found to come up as 3. This means FIMD SYSMMU is on by
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* default on Exynos5420. For now we are disabling FIMD SYSMMU.
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*/
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writel(0x0, (void *)0x14640000);
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writel(0x0, (void *)0x14680000);
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lcd_vdd();
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/* Start the fimd running before you do the phy and lcd setup.
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* why do fimd before training etc?
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* because we need a data stream from
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* the fimd or the clock recovery step fails.
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*/
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vidinfo.screen_base = fb_addr;
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exynos_fimd_lcd_init(&vidinfo);
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parade_dp_bridge_setup();
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dp_controller_init(&dp_device);
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/* this might get more dynamic in future ... */
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memset(&device_info, 0, sizeof(device_info));
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device_info.disp_info.name = (char *)"Kirby display";
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device_info.disp_info.h_total = 1366;
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device_info.disp_info.v_total = 768;
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device_info.video_info = dp_video_info;
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device_info.raw_edid = panel_edid;
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exynos_init_dp(&device_info);
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udelay(LCD_T3_DELAY_MS * 1000);
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backlight_vdd();
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backlight_pwm();
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// Uncomment to get excessive GPIO output:
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// gpio_info();
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}
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static void mainboard_enable(device_t dev)
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@ -43,6 +43,8 @@
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#define MMC0_GPIO_PIN (58)
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#define PMIC_I2C_BUS 4
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struct pmic_write
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{
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int or_orig; // Whether to or in the original value.
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@ -60,7 +62,7 @@ struct pmic_write pmic_writes[] =
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{ 0, MAX77802_REG_PMIC_BUCK1DVS1, MAX77802_BUCK1DVS1_1V },
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{ 1, MAX77802_REG_PMIC_BUCK1CTRL, MAX77802_BUCK_TYPE1_ON |
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MAX77802_BUCK_TYPE1_IGNORE_PWRREQ },
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{ 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1V },
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{ 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1_2625V },
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{ 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON |
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MAX77802_BUCK_TYPE2_IGNORE_PWRREQ },
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{ 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V },
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@ -72,10 +74,11 @@ struct pmic_write pmic_writes[] =
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{ 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V },
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{ 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON |
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MAX77802_BUCK_TYPE1_IGNORE_PWRREQ },
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{ 1, MAX77802_REG_PMIC_LDO35CTRL1, MAX77802_LDO35CTRL1_1_2V },
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/* Disable Boost(bypass) OUTPUT */
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{ 0, MAX77802_REG_PMIC_BOOSTCTRL, MAX77802_BOOSTCTRL_OFF},
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};
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static void setup_power(int is_resume)
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static int setup_power(int is_resume)
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{
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int error = 0;
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int i;
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@ -83,14 +86,12 @@ static void setup_power(int is_resume)
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power_init();
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if (is_resume) {
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return;
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return 0;
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}
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/* Initialize I2C bus to configure PMIC. */
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exynos_pinmux_i2c4();
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i2c_init(4, 1000000, 0x00); /* 1MHz */
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printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__);
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i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */
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for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) {
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uint8_t data = 0;
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@ -106,8 +107,7 @@ static void setup_power(int is_resume)
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&data, sizeof(data));
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}
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if (error)
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die("Failed to intialize PMIC.\n");
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return error;
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}
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static void setup_storage(void)
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@ -245,6 +245,7 @@ void main(void)
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extern struct mem_timings mem_timings;
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void *entry;
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int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
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int power_init_failed;
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#if CONFIG_COLLECT_TIMESTAMPS
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uint64_t start_romstage_time;
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uint64_t before_dram_time;
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@ -253,14 +254,22 @@ void main(void)
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start_romstage_time = timestamp_get();
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#endif
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exynos5420_config_smp();
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power_init_failed = setup_power(is_resume);
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/* Clock must be initialized before console_init, otherwise you may need
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* to re-initialize serial console drivers again. */
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system_clock_init();
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exynos_pinmux_uart3();
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console_init();
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setup_power(is_resume);
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if (power_init_failed)
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die("Failed to intialize power.\n");
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/* re-initialize PMIC I2C channel after (re-)setting system clocks */
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i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */
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#if CONFIG_COLLECT_TIMESTAMPS
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before_dram_time = timestamp_get();
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#endif
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