From 2f2c9ce2ad7b61e7719672a539f0e1adff0b490b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 13 Aug 2013 21:28:55 -0700 Subject: [PATCH] kirby: Update kirby and get it to build again. Update the kirby mainboard files so they build again and are current with pit. BUG=chrome-os-partner:19420 TEST=Built for kirby. BRANCH=None Change-Id: Ie6d9fcd4e620d2d82b4b2083b713d64e6e72d55e Signed-off-by: Gabe Black Reviewed-on: https://gerrit.chromium.org/gerrit/65936 Reviewed-by: Ronald G. Minnich Tested-by: Gabe Black Commit-Queue: Gabe Black --- src/mainboard/google/kirby/mainboard.c | 128 +++++++++++++++++++++---- src/mainboard/google/kirby/romstage.c | 29 ++++-- 2 files changed, 128 insertions(+), 29 deletions(-) diff --git a/src/mainboard/google/kirby/mainboard.c b/src/mainboard/google/kirby/mainboard.c index 777b9c3859..c671f9df04 100644 --- a/src/mainboard/google/kirby/mainboard.c +++ b/src/mainboard/google/kirby/mainboard.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -34,6 +35,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +54,64 @@ static struct edid edid = { .bytes_per_line = 2 * 1366 }; +/* from the fdt */ +static struct vidinfo vidinfo = { + .vl_freq = 60, + .vl_col = 1366, + .vl_row = 768, + .vl_width = 1366, + .vl_height = 768, + .vl_clkp = 1, + .vl_dp = 1, + .vl_bpix = 4, + .vl_hspw = 32, + .vl_hbpd = 40, + .vl_hfpd = 40, + .vl_vspw = 6, + .vl_vbpd = 10, + .vl_vfpd = 12, + .vl_cmd_allow_len = 0xf, + .win_id = 3, + .dp_enabled = 1, + .dual_lcd_enabled = 0, + .interface_mode = FIMD_RGB_INTERFACE, +}; + +static unsigned char panel_edid[] = { + 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00, + 0x06,0xaf,0x5c,0x31,0x00,0x00,0x00,0x00, + 0x00,0x16,0x01,0x03,0x80,0x1a,0x0e,0x78, + 0x0a,0x99,0x85,0x95,0x55,0x56,0x92,0x28, + 0x22,0x50,0x54,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, + 0x01,0x01,0x01,0x01,0x01,0x01,0xa3,0x1b, + 0x56,0x7e,0x50,0x00,0x16,0x30,0x30,0x20, + 0x36,0x00,0x00,0x90,0x10,0x00,0x00,0x18, + 0x6d,0x12,0x56,0x7e,0x50,0x00,0x16,0x30, + 0x30,0x20,0x36,0x00,0x00,0x90,0x10,0x00, + 0x00,0x18,0x00,0x00,0x00,0xfe,0x00,0x41, + 0x55,0x4f,0x0a,0x20,0x20,0x20,0x20,0x20, + 0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xfe, + 0x00,0x42,0x31,0x31,0x36,0x58,0x57,0x30, + 0x33,0x20,0x56,0x31,0x20,0x0a,0x00,0x3d, + 0x00,0xc0,0x00,0x00,0x27,0xfd,0x00,0x20, + 0x02,0x59,0x07,0x00,0x64,0x3e,0x07,0x02, + 0x00,0x00,0xcd,0x12,0x59,0xff,0x10,0x03, + 0x00,0x00,0x00,0x00,0x64,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x05,0x00,0x00,0x00, + 0x9c,0x3f,0x07,0x02,0x31,0xf9,0x00,0x20, + 0x59,0xff,0x10,0x03,0x00,0x00,0x00,0x00, + 0xbc,0x3e,0x07,0x02,0xc0,0x9b,0x01,0x20, + 0x00,0x00,0x00,0x00,0xdb,0xf8,0x00,0x20, + 0x98,0x3e,0x07,0x02,0x8b,0xaf,0x00,0x20, + 0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0xe5,0xcd,0x16,0x00,0xe9,0xcd,0x16,0x00, + 0xe8,0x03,0x00,0x00,0x6c,0x55,0x01,0x20, + 0x2c,0x01,0x00,0x00,0x85,0xbb,0x00,0x20, + 0xe8,0x03,0x00,0x00,0xe9,0xcd,0x16,0x00, +}; + static const struct parade_write parade_writes[] = { { 0x02, 0xa1, 0x01 }, /* HPD low */ /* @@ -175,6 +235,8 @@ static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */ static void parade_dp_bridge_setup(void) { + int i; + gpio_set_value(dp_pd_l, 1); gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); gpio_set_pull(dp_pd_l, GPIO_PULL_NONE); @@ -185,6 +247,8 @@ static void parade_dp_bridge_setup(void) udelay(10); gpio_set_value(dp_rst_l, 1); + + gpio_set_pull(dp_hpd, GPIO_PULL_NONE); gpio_cfg_pin(dp_hpd, GPIO_INPUT); /* De-assert PD (and possibly RST) to power up the bridge. */ @@ -198,9 +262,19 @@ static void parade_dp_bridge_setup(void) exynos_pinmux_i2c7(); i2c_init(7, 100000, 0x00); - parade_ps8625_bridge_setup(7, 0x48, - parade_writes, + parade_ps8625_bridge_setup(7, 0x48, parade_writes, ARRAY_SIZE(parade_writes)); + /* Spin until the display is ready. + * It's quite important to try really hard to get the display up, + * so be generous. It will typically be ready in only 5 ms. and + * we're out of here. + * If it's not ready after a second, then we're in big trouble. + */ + for(i = 0; i < 1000; i++){ + if (gpio_get_value(dp_hpd)) + break; + mdelay(1); + } } /* @@ -223,22 +297,17 @@ static void backlight_pwm(void) udelay(LCD_T6_DELAY_MS * 1000); } -//static struct video_info smdk5420_dp_config = { -static struct video_info dp_video_info = { - /* FIXME: fix video_info struct to use const for name */ - .name = (char *)"eDP-LVDS NXP PTN3460", + +static struct edp_video_info dp_video_info = { + .master_mode = 0, .h_sync_polarity = 0, .v_sync_polarity = 0, .interlaced = 0, - .color_space = COLOR_RGB, .dynamic_range = VESA, .ycbcr_coeff = COLOR_YCBCR601, .color_depth = COLOR_8, - - .link_rate = LINK_RATE_2_70GBPS, - .lane_count = LANE_COUNT2, }; /* FIXME: move some place more appropriate */ @@ -277,14 +346,13 @@ static void backlight_vdd(void) /* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { - struct s5p_dp_device dp_device = { - .base = (struct exynos5_dp *)EXYNOS5420_DP1_BASE, - .video_info = &dp_video_info, - }; + /* we'll stick with the crummy u-boot struct for now.*/ + /* doing this as an auto since the struct has to be writeable */ + struct edp_device_info device_info; + void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); - tmu_init(&exynos5420_tmu_info); /* Clock Gating all the unused IP's to save power */ @@ -295,18 +363,40 @@ static void mainboard_init(device_t dev) set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); + /* + * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000 + * should be 0 according to the datasheet, but has experimentally + * been found to come up as 3. This means FIMD SYSMMU is on by + * default on Exynos5420. For now we are disabling FIMD SYSMMU. + */ + writel(0x0, (void *)0x14640000); + writel(0x0, (void *)0x14680000); + lcd_vdd(); + /* Start the fimd running before you do the phy and lcd setup. + * why do fimd before training etc? + * because we need a data stream from + * the fimd or the clock recovery step fails. + */ + vidinfo.screen_base = fb_addr; + exynos_fimd_lcd_init(&vidinfo); + parade_dp_bridge_setup(); - dp_controller_init(&dp_device); + + /* this might get more dynamic in future ... */ + memset(&device_info, 0, sizeof(device_info)); + device_info.disp_info.name = (char *)"Kirby display"; + device_info.disp_info.h_total = 1366; + device_info.disp_info.v_total = 768; + device_info.video_info = dp_video_info; + device_info.raw_edid = panel_edid; + exynos_init_dp(&device_info); udelay(LCD_T3_DELAY_MS * 1000); backlight_vdd(); backlight_pwm(); - - // Uncomment to get excessive GPIO output: - // gpio_info(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/kirby/romstage.c b/src/mainboard/google/kirby/romstage.c index c277ad4d15..a4e69d5714 100644 --- a/src/mainboard/google/kirby/romstage.c +++ b/src/mainboard/google/kirby/romstage.c @@ -43,6 +43,8 @@ #define MMC0_GPIO_PIN (58) +#define PMIC_I2C_BUS 4 + struct pmic_write { int or_orig; // Whether to or in the original value. @@ -60,7 +62,7 @@ struct pmic_write pmic_writes[] = { 0, MAX77802_REG_PMIC_BUCK1DVS1, MAX77802_BUCK1DVS1_1V }, { 1, MAX77802_REG_PMIC_BUCK1CTRL, MAX77802_BUCK_TYPE1_ON | MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, - { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1V }, + { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1_2625V }, { 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, { 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V }, @@ -72,10 +74,11 @@ struct pmic_write pmic_writes[] = { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V }, { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON | MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, - { 1, MAX77802_REG_PMIC_LDO35CTRL1, MAX77802_LDO35CTRL1_1_2V }, + /* Disable Boost(bypass) OUTPUT */ + { 0, MAX77802_REG_PMIC_BOOSTCTRL, MAX77802_BOOSTCTRL_OFF}, }; -static void setup_power(int is_resume) +static int setup_power(int is_resume) { int error = 0; int i; @@ -83,14 +86,12 @@ static void setup_power(int is_resume) power_init(); if (is_resume) { - return; + return 0; } /* Initialize I2C bus to configure PMIC. */ exynos_pinmux_i2c4(); - i2c_init(4, 1000000, 0x00); /* 1MHz */ - - printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); + i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { uint8_t data = 0; @@ -106,8 +107,7 @@ static void setup_power(int is_resume) &data, sizeof(data)); } - if (error) - die("Failed to intialize PMIC.\n"); + return error; } static void setup_storage(void) @@ -245,6 +245,7 @@ void main(void) extern struct mem_timings mem_timings; void *entry; int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); + int power_init_failed; #if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; @@ -253,14 +254,22 @@ void main(void) start_romstage_time = timestamp_get(); #endif + exynos5420_config_smp(); + power_init_failed = setup_power(is_resume); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ system_clock_init(); + exynos_pinmux_uart3(); console_init(); - setup_power(is_resume); + if (power_init_failed) + die("Failed to intialize power.\n"); + + /* re-initialize PMIC I2C channel after (re-)setting system clocks */ + i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ + #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); #endif