From 2ee72eaab12f578caedaf69c950b57800e547ec4 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 12 Jun 2025 17:27:02 +0530 Subject: [PATCH] soc/intel/pantherlake: Update CONSOLE_UART_BASE_ADDRESS Kconfig value The console UART base address for Panther Lake is being updated from 0xfe02c000 to 0xfe036000 (as per FSP version 3182). This correction ensures the console initializes with the correct UART base address. Additionally, now the UART base address is in sync between coreboot, FSP and GFX PEIM. BUG=b:423878608 TEST=Able to get FSP debug log while building google/fatcat. ``` dw-apb-uart.3: ttyS0 at MMIO 0xfe036000 ``` Change-Id: I0caae8b5ea34561d88f5a4aa0cb12481db6f9417 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/88073 Reviewed-by: Reviewed-by: Pranava Y N Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 03865b2ddf..87d78b85a2 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -308,7 +308,7 @@ config SOC_INTEL_USB3_DEV_MAX config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe02c000 + default 0xfe036000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate