reduce size of the ipl.S in northbridge/acer/m1631.
There is a problem with memory settings, however.
This commit is contained in:
Ronald G. Minnich
parent
320da3eb72
commit
2dea4d84d5
2 changed files with 70 additions and 54 deletions
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@ -18,7 +18,7 @@ it with the version available from LANL.
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*/
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/* Parts of this code Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
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* rminnich@lanl.gov
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* Modifications by Ronnie Liu of Acer Labs Inc.
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* Modifications by Ronnie Liu of Acer Labs Inc.
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*/
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#include <asm.h>
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#include <cpu/p5/macros.h>
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@ -39,15 +39,23 @@ it with the version available from LANL.
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* ror it 16 bits, and as we grow the CAS, we just inc cs, and that will
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* set the right value.
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*/
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#define INIT_MCR $0xf6411000
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#define INIT_MCR $0xf6621000
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#define WRITE_MCR0 movl %ecx, %eax ; outl %eax, %dx
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/*#include <cpu/p5/start32.inc>*/
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.org 0xfe000
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.code16
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_start: jmp _realstart
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gdt: //GDT entry 0 (null segment)
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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// this GDT 0 is garbage. But we won't ever use it, so
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// that's ok.
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bytes:
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// these first two bytes are for flash. It's ugly,
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// but we are out of room!
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.byte 0xff, NO_INB, 0x40
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.byte 0xf8, 0xfd, NO_INB, 0x8
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.byte 0x8c, 0xfe, DO_INB, 0x8
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.byte 0x80, 0xfe, NO_INB, 0x10
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.byte 0
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// GDT 1
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x0, 0x9a, 0xcf, 0x0
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@ -59,23 +67,16 @@ gdtptr:
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.word 4*8-1
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.long gdt /* we know the offset */
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.long 0
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#define DO_INB 1
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#define NO_INB 0
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bytes:
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.byte 0xf8, 0xfd, NO_INB, 0x8
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.byte 0x8c, 0xfe, DO_INB, 0x8
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.byte 0x48, 0xfd, NO_INB, 0x60
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.byte 0x80, 0xfe, NO_INB, 0x10
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.byte 0x90, 0xff, DO_INB, 0x6
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.byte 0x80, 0xff, NO_INB, 0
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.byte 0
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_realstart:
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cli
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movw %cs, %ax
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movw %ax, %es
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.byte 0x66 /* prefix */
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.byte 0x26
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.byte 0x0f, 0x01, 0x16 /* lgdt [es:offset]*/
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@ -93,11 +94,11 @@ _realstart:
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.Lprotected:
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.code32
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movw $0x18, %bx
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movw %bx, %es
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/* movw %bx, %es*/
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movw %bx, %ds
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movw %bx, %es
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movw %bx, %fs
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movw %bx, %gs
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/* movw %bx, %es*/
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/* movw %bx, %fs*/
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/* movw %bx, %gs*/
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movw %bx, %ss
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#ifdef USE_BIG_REAL
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andb $0xfe, %al
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@ -113,21 +114,19 @@ code16
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movl $0x80003844, %eax
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mov $0x0cf8,%dx
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outl %eax,%dx
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/* but 0x40 makes flash writeable. You need this for DoC */
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movb $0x40, %al
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/* 0xff selects register 0x47 */
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movb $0xff, %dl
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outb %al,%dx
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xorl %edi, %edi
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xorw %ax,%ax
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movl $bytes, %esi
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/* Must set regs on North Bridge */
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movb $0xc, %dh
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movb (%esi), %al
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jmp selectbyte
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loop:
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movb $0xf8, %dl
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inc %esi
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outl %eax,%dx
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// from here, you are selecting which byte to use.
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selectbyte:
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movb (%esi),%dl
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inc %esi
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movb (%esi),%al
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@ -147,6 +146,7 @@ noinb:
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cmpb $0, %al
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jne loop
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/* Must set regs on North Bridge (device 0) */
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movb $0x6c, %al
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movb $0xf8,%dl
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@ -154,33 +154,40 @@ noinb:
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/* movb $0x8000006c, %al
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CALLSP(pci_read_dword)*/
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movb $0xfc, %dl
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inl %dx, %eax
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movl %eax, %ecx
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andl $0xfffc, %ecx
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orl INIT_MCR, %ecx
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movl $0xf662f83c, %ecx
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WRITE_MCR0
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/* check for registered. All this means is write to 0,
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* read back, if it's not the same, set 'registered',
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* read back, it it's the same you're ok.
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*/
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movb $0xa5, (%edi)
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cmpb $0xa5, (%edi)
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je nonregistered
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orb $0x40, %cl
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WRITE_MCR0
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/*
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movb $0x6c, %al
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CALLSP(pci_write_dword)
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*/
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nonregistered:
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rorl $16, %ecx
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/* clear out the CAS, since we assume start at zero
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* and increment
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*/
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andb $0xf0, %cl
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/* test 8 bit CAS */
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movb $0, 0
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movb $0, (%edi)
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movb $1, 0x800
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cmpb $0,0
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cmpb $0,(%edi)
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jnz sizeram
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inc %cl
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/* change the value we store each time. It makes debugging easier */
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movb $2, 0x1000
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cmpb $0, 0
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cmpb $0, (%edi)
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jnz sizeram
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inc %cl
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movb $3, 0x2000
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cmpb $0, 0
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cmpb $0, (%edi)
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jnz sizeram
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inc %cl
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@ -188,7 +195,7 @@ sizeram:
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rorl $16, %ecx
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/* clear the 'no multi page' bit. */
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andw $0xefff, %cx
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WRITE_MCR0
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WRITE_MCR0
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/*
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mov $0x6c, %al
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CALLSP(pci_write_dword)
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@ -197,7 +204,7 @@ sizeram:
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/* now size the dram */
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/* you had best have at least 4M; that's as small as we go */
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/* rorr 20 the ecx value, to get row size into lsb */
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movb $0, 0
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movb $0, (%edi)
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ror $20, %ecx
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/* clear the size out to 4 MB */
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andb $0xf8, %cl
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@ -212,7 +219,7 @@ sizeram:
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*/
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movb $4, %es:(%esi)
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#endif
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cmpb $0, 0
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cmpb $0, (%edi)
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/* if there is not a 0 at 0, the last write wrapped. Hop out */
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jne 1f
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inc %cl
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@ -234,21 +241,22 @@ sizeram:
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* Just set 4-bank mode, and set non-zero numbers into a few places.
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* if the byte at 0 changes, you have two banks. Trivial.
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*/
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movb $0, 0
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movb $0, (%edi)
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movb $5, 0x1000
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movb $6, 0x2000
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movb $7, 0x4000
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cmpb $0, 0
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jz 1f /* only one bank */
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cmpb $0, (%edi)
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jz 1f /* 4 banks */
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orl $0x80000, %ecx
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1:
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/* clear 4 banks */
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andb $0xfe, %cl
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1:
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WRITE_MCR0
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movl $0x8000007c, %eax
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movb $0xf8, %dl
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outl %eax, %dx
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movl $0x242bc411, %eax
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movl $0x2428c411, %eax
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movb $0xfc, %dl
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outl %eax, %dx
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/*
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@ -262,11 +270,6 @@ sizeram:
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/* INPUT: %al, the register. %ecx, the write data */
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/* Following code courtesy Ollie Lho: */
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/*
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@ -401,6 +404,7 @@ doc_cycle_end:
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/* we don't need these. We only do I/O to MCR 0 */
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#if 0
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pci_write_dword:
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mov $0,%ah
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mov $0x80000000,%edx
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@ -423,6 +427,7 @@ pci_read_dword:
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inl %dx, %eax
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mov %eax, %ecx
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RETSP
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#endif
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.org 0xfe1f0
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reset_vector:
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@ -89,6 +89,7 @@ _realstart:
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movw %bx, %fs
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movw %bx, %gs
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movw %bx, %ss
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xorl %edi, %edi
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#ifdef USE_BIG_REAL
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andb $0xfe, %al
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movl %eax, %cr0
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@ -141,28 +142,38 @@ code16
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movb $0xfc, %dl
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movl $0xf662f83c, %ecx
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WRITE_MCR0
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/* check for registered. All this means is write to 0,
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* read back, if it's not the same, set 'registered',
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* read back, it it's the same you're ok.
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*/
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movb $0xa5, (%edi)
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cmpb $0xa5, (%edi)
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je nonregistered
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orb $0x40, %cl
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WRITE_MCR0
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/*
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movb $0x6c, %al
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CALLSP(pci_write_dword)
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*/
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nonregistered:
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rorl $16, %ecx
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/* clear out the CAS, since we assume start at zero
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* and increment
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*/
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andb $0xf0, %cl
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/* test 8 bit CAS */
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movb $0, 0
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movb $0, (%edi)
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movb $1, 0x800
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cmpb $0,0
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cmpb $0,(%edi)
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jnz sizeram
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inc %cl
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/* change the value we store each time. It makes debugging easier */
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movb $2, 0x1000
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cmpb $0, 0
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cmpb $0, (%edi)
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jnz sizeram
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inc %cl
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movb $3, 0x2000
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cmpb $0, 0
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cmpb $0, (%edi)
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jnz sizeram
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inc %cl
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@ -179,7 +190,7 @@ sizeram:
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/* now size the dram */
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/* you had best have at least 4M; that's as small as we go */
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/* rorr 20 the ecx value, to get row size into lsb */
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movb $0, 0
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movb $0, (%edi)
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ror $20, %ecx
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/* clear the size out to 4 MB */
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andb $0xf8, %cl
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@ -194,7 +205,7 @@ sizeram:
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*/
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movb $4, %es:(%esi)
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#endif
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cmpb $0, 0
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cmpb $0, (%edi)
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/* if there is not a 0 at 0, the last write wrapped. Hop out */
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jne 1f
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inc %cl
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@ -216,11 +227,11 @@ sizeram:
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* Just set 4-bank mode, and set non-zero numbers into a few places.
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* if the byte at 0 changes, you have two banks. Trivial.
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*/
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movb $0, 0
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movb $0, (%edi)
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movb $5, 0x1000
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movb $6, 0x2000
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movb $7, 0x4000
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cmpb $0, 0
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cmpb $0, (%edi)
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jz 1f /* 4 banks */
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orl $0x80000, %ecx
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/* clear 4 banks */
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