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Fixes for autosize

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This commit is contained in:
Ronald G. Minnich 2001-03-15 20:25:30 +00:00
commit 320da3eb72
2 changed files with 17 additions and 71 deletions
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9
src/northbridge/acer/m1631/chipset_init.inc
View file

@ -35,6 +35,7 @@ register_table:
.byte 0x80, 0xf9, 0x01
.byte 0x81, 0xb3, 0x00
.byte 0x82, 0xff, 0x10
.byte 0x83, 0x00, 0x00
.byte 0x84, 0xfe, 0x00
.byte 0x87, 0xff, 0x00
.byte 0x88, 0xff, 0x08
@ -59,8 +60,7 @@ register_table:
.byte 0xd9, 0xff, 0x03
.byte 0xdc, 0x00, 0x10
.byte 0xde, 0xff, 0x04
.byte 0xf9, 0xff, 0x4
.byte 0xf0, 0x00, 0x50
.byte 0xf0, 0x00, 0x54
.byte 0xf1, 0x00, 0x04
.byte 0xf2, 0x00, 0x09
.byte 0xf3, 0x00, 0x1f
@ -77,9 +77,12 @@ register_table:
.byte 0x0 /* end of table */
m1535_table:
.byte 0x41, 0x00, 0x0d // enable superIO recovery
.byte 0x47, 0xff, 0x40 // enable flash rom r/w
.byte 0x44, 0x00, 0x5d // set edge mode, primary channel IRQ 14
.byte 0x75, 0x00, 0x0f // secondary channel 15
.byte 0x75, 0x00, 0x0f // secondary channel IRQ 15
.byte 0x58, 0x00, 0x4c // enable IDE controller
.byte 0x70, 0x00, 0x12 // set serial IRQ data frame
.byte 0x0 // end of m1535_table
chipsetinit_start:

79
src/northbridge/acer/m1631/ipl.S
View file

@ -18,7 +18,7 @@ it with the version available from LANL.
*/
/* Parts of this code Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
* rminnich@lanl.gov
* Modifications by Ronnie Liu of Acer Labs Inc.
* Modifications by Ronnie Liu of Acer Labs Inc.
*/
#include <asm.h>
#include <cpu/p5/macros.h>
@ -108,13 +108,11 @@ code16
/* 0xff selects register 0x47 */
movb $0xff, %dl
outb %al,%dx
xorl %edi, %edi
/* Must set regs on North Bridge (device 0) */
/* Must set regs on North Bridge */
movl $0x800000f8,%eax /* f9h */
movw $0xcf8,%dx
movw $0x00f8,%ax /* f9h */
movb $0xf8,%dl
outl %eax,%dx
movb $0xfd,%dl
movb $0x08,%al
@ -128,13 +126,6 @@ code16
orb $0x08,%al
outb %al,%dx
movb $0x48,%al /* 49h */
movb $0xf8,%dl
outl %eax,%dx
movb $0xfd,%dl
movb $0x60,%al
outb %al,%dx
movb $0x80,%al /* 82h */
movb $0xf8,%dl
outl %eax,%dx
@ -142,57 +133,13 @@ code16
movb $0x10,%al
outb %al,%dx
movb $0x90,%al /* 93h */
movb $0x6c, %al
movb $0xf8,%dl
outl %eax,%dx
movb $0xff,%dl
inb %dx,%al
orb $0x06,%al
outb %al,%dx
movb $0x80,%al /* 83h */
movb $0xf8,%dl
outl %eax,%dx
movb $0xff,%dl
movb $0x00,%al
outb %al,%dx
movb $0x6c,%al /* 6eh, 6fh */
movb $0xf8,%dl
outl %eax,%dx
movb $0xfc, %dl
inl %dx, %eax
andl $0x0000fffc, %eax
orl $0xf6410001, %eax
outl %eax, %dx
movb $0x55, 0
movb $0xaa, 0x2000
cmpb $0x55, 0
je bank_4
andb $0xfc, %al /* 2 bank */
bank_4:
outl %eax, %dx
movl $0x8000007c,%eax /* Enable Refresh 7eh */
movw $0xcf8,%dx
outl %eax,%dx
movb $0xfe,%dl
inb %dx,%al
orb $0x08,%al
outb %al,%dx
#if 0
movl $0x8000006c, %eax
mov $0x0cf8,%dx
outl %eax,%dx
/* movb $0x8000006c, %al
CALLSP(pci_read_dword)*/
movb $0xfc, %dl
inl %dx, %eax
movl %eax, %ecx
andl $0xfffc, %ecx
orl INIT_MCR, %ecx
movl $0xf662f83c, %ecx
WRITE_MCR0
/*
movb $0x6c, %al
@ -223,7 +170,7 @@ sizeram:
rorl $16, %ecx
/* clear the 'no multi page' bit. */
andw $0xefff, %cx
WRITE_MCR0
WRITE_MCR0
/*
mov $0x6c, %al
CALLSP(pci_write_dword)
@ -274,16 +221,17 @@ sizeram:
movb $6, 0x2000
movb $7, 0x4000
cmpb $0, 0
jz 1f /* only one bank */
jz 1f /* 4 banks */
orl $0x80000, %ecx
1:
/* clear 4 banks */
andb $0xfe, %cl
1:
WRITE_MCR0
movl $0x8000007c, %eax
movb $0xf8, %dl
outl %eax, %dx
movl $0x242bc411, %eax
movl $0x2428c411, %eax
movb $0xfc, %dl
outl %eax, %dx
/*
@ -297,11 +245,6 @@ sizeram:
/* INPUT: %al, the register. %ecx, the write data */
/* Following code courtesy Ollie Lho: */
#endif
/*