From 2d3ec06ec39a489d02e798bb22bce4d7465b20ce Mon Sep 17 00:00:00 2001
From: Hung-Te Lin <hungte@chromium.org>
Date: Thu, 12 Dec 2013 19:45:52 +0800
Subject: [PATCH] tegra124: Run bootblock and ROM stage out of DRAM.

To allow doing DRAM initialization in ROM stage instead of BootROM, we need to
move bootblock and ROM stage base address into iRAM, also the stack and CBFS
cache area just like TTB.

BUG=none
TEST=Boots on Nyan without problem.

Change-Id: I459faef5eb0f75561089dafbb111ae83729c3a29
Reviewed-on: https://chromium-review.googlesource.com/179822
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
---
 src/soc/nvidia/tegra124/Kconfig | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 024dfe3734..23f48f2c0d 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -32,8 +32,14 @@ config BOOTBLOCK_CPU_INIT
 # 0x4000_0000 BootROM runtime data/stack area, can be reclaimed after BootROM.
 #       +0000 (BootROM) Boot Information Table.
 #       +0100 (BootROM) BCT.
+#       ---------------------------------------------------------------------
+#       +0000 (Coreboot) TTB 16KB.
+#       +4000 (Coreboot) Stack.
 # 0x4000_E000 Valid for anything to be executed after BootROM (effective entry
 #             point address specified in BCT).
+#       +0000 (Coreboot) Bootblock (max 36k).
+#       +9000 (Coreboot) ROM stage (max 36k).
+# 0x4002_0000 (Coreboot) Cache of CBFS.
 # 0x4003_FFFF End of iRAM.
 
 config BOOTBLOCK_ROM_OFFSET
@@ -54,11 +60,11 @@ config SYS_SDRAM_BASE
 
 config BOOTBLOCK_BASE
 	hex
-	default 0x80000000
+	default 0x4000e000
 
 config ROMSTAGE_BASE
 	hex
-	default 0x80100000
+	default 0x40017000
 
 config RAMSTAGE_BASE
 	hex
@@ -66,11 +72,11 @@ config RAMSTAGE_BASE
 
 config STACK_TOP
 	hex
-	default 0x80400000
+	default 0x4000c000
 
 config STACK_BOTTOM
 	hex
-	default 0x803f8000
+	default 0x40004000
 
 config STACK_SIZE
 	hex
@@ -83,7 +89,7 @@ config TTB_BUFFER
 
 config CBFS_CACHE_ADDRESS
 	hex "memory address to put CBFS cache data"
-	default 0x803c0000
+	default 0x40020000
 
 config CBFS_CACHE_SIZE
 	hex "size of CBFS cache data"