From 2ac2df0edaa75eb88333e231344cb0db801045d7 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 27 Feb 2026 23:56:38 +0100 Subject: [PATCH] sb/intel/wildcatpoint/pcie.c: Reorder some steps Run some steps a bit earlier for consistency with Lynx Point. Change-Id: I819f95275b23867c83d0991f1eaab3d2e8947abc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/91473 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/southbridge/intel/wildcatpoint/pcie.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c index 1af776d7d8..37d24ef2ee 100644 --- a/src/southbridge/intel/wildcatpoint/pcie.c +++ b/src/southbridge/intel/wildcatpoint/pcie.c @@ -538,6 +538,12 @@ static void pch_pcie_early(struct device *dev) pci_and_config8(dev, 0xf5, 0x0f); + if (rp == 1 || rp == 5 || rp == 6) + pci_and_config8(dev, 0xf7, ~0x0c); + + /* Set EOI forwarding disable. */ + pci_or_config32(dev, 0xd4, 1 << 1); + /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ if (CONFIG(PCIEXP_AER)) pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001); @@ -555,12 +561,6 @@ static void pch_pcie_early(struct device *dev) /* Enable Relaxed Order from Root Port. */ pci_or_config32(dev, 0x320, 3 << 23); - if (rp == 1 || rp == 5 || rp == 6) - pci_update_config8(dev, 0xf7, ~0xc, 0); - - /* Set EOI forwarding disable. */ - pci_update_config32(dev, 0xd4, ~0, (1 << 1)); - /* Read and write back write-once capability registers. */ pci_update_config32(dev, 0x34, ~0, 0); pci_update_config32(dev, 0x40, ~0, 0);