From 289cff34235e367b42dfad21182f672849574aea Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 30 Jun 2022 21:22:59 +0100
Subject: [PATCH] soc/intel/apollolake: Load the IBB into CAR

Copy the IBB into CAR via the CSEs RBP to ensure it has not been
modified.

Test on the StarLite Mk III and Mk IV:
Without VBOOT:
    [DEBUG]  CSE: IBB Verification Result: PASS
    [DEBUG]  CSE: IBB Verification Done  : YES
    [DEBUG]  CSE: IBB Size               : 88

With VBOOT:
    [DEBUG]  CSE: IBB Verification Result: PASS
    [DEBUG]  CSE: IBB Verification Done  : YES
    [DEBUG]  CSE: IBB Size               : 102

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0d4e26834cef4c876e37e414b424a031c11111ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 090bd5071d..cb1dd20a2c 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -15,8 +15,9 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
-#include <soc/iomap.h>
 #include <soc/cpu.h>
+#include <soc/loader.h>
+#include <soc/gpio.h>
 #include <soc/soc_chip.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>
@@ -55,6 +56,11 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 
 	enable_rtc_upper_bank();
 
+	if (CONFIG(IFWI_IBBM_LOAD)) {
+		load_ibb(CONFIG_IBBM_ROM_ADDR, CONFIG_IBBM_ROM_SIZE);
+		flush_l1d_to_l2();
+	}
+
 	/* Call lib/bootblock.c main */
 	bootblock_main_with_basetime(base_timestamp);
 }