From 2783d233d6b202d6d59255143a2c6ab64a6c0f97 Mon Sep 17 00:00:00 2001 From: Andrew Ip Date: Sat, 14 Dec 2002 06:34:34 +0000 Subject: [PATCH] Kevin Hester , fixed irq assignment --- src/mainboard/via/epia/Config | 14 +- src/mainboard/via/epia/irq_tables.c | 27 +- src/mainboard/via/epia/mainboard.c | 72 ++-- src/southbridge/via/vt8231/ideconfig.inc | 9 + src/southbridge/via/vt8231/southbridge.c | 409 +++++++++++++++------- src/superio/via/vt8231/setup_ethernet.inc | 13 +- 6 files changed, 359 insertions(+), 185 deletions(-) create mode 100644 src/southbridge/via/vt8231/ideconfig.inc diff --git a/src/mainboard/via/epia/Config b/src/mainboard/via/epia/Config index 66c7b868dd..5041f35f2f 100644 --- a/src/mainboard/via/epia/Config +++ b/src/mainboard/via/epia/Config @@ -6,11 +6,12 @@ ldscript cpu/i386/entry32.lds mainboardinit cpu/i386/reset16.inc ldscript cpu/i386/reset16.lds -mainboardinit superio/via/vt8231/setup_serial.inc mainboardinit superio/via/vt8231/setup_ethernet.inc +mainboardinit superio/via/vt8231/setup_serial.inc mainboardinit pc80/serial.inc mainboardinit arch/i386/lib/console.inc mainboardinit northbridge/via/vt8601/raminit.inc +mainboardinit southbridge/via/vt8231/ideconfig.inc # mainboardinit ram/dump_northbridge.inc # mainboardinit ram/ramtest.inc # mainboardinit mainboard/via/epia/do_ramtest.inc @@ -21,18 +22,21 @@ southbridge via/vt8231 # kevinh - this doesn't build correctly, and I think it is just duplicating # the functionality of some of the early setup. # superio via/vt8231 +mainboardinit cpu/c3/premtrr.inc mainboardinit cpu/p6/earlymtrr.inc -# The 8231 includes built in Ethernet, however it must be enabled BEFORE -# the PCI enumeration so that it can be set up. -option ENABLE_VT8231_LAN=1 option ENABLE_FIXED_AND_VARIABLE_MTRRS=1 option FINAL_MAINBOARD_FIXUP=1 option HAVE_PIRQ_TABLE=1 option SUPERIO_DEVFN=0x88 -option IOAPIC=1 +option ENABLE_VT8231_LAN=1 +option ENABLE_VT8231_USB=1 +# 021214 aip - irq has problem with native mode, so make sure it is disabled. +option ENABLE_IDE_NATIVE_MODE=0 + object irq_tables.o object mainboard.o + keyboard pc80 cpu p5 cpu p6 diff --git a/src/mainboard/via/epia/irq_tables.c b/src/mainboard/via/epia/irq_tables.c index b8b3379ce1..894c27dec5 100644 --- a/src/mainboard/via/epia/irq_tables.c +++ b/src/mainboard/via/epia/irq_tables.c @@ -11,19 +11,22 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*5, /* there can be total 5 devices on the bus */ - 0, /* Where the interrupt router lies (bus) */ - 0, /* Where the interrupt router lies (dev) */ - 0xc20, /* IRQs devoted exclusively to PCI usage */ - 0, /* Vendor */ - 0, /* Device */ - 0, /* Crap (miniport) */ + 0, /* Where the interrupt router lies (bus) */ + 0x88, /* Where the interrupt router lies (dev) */ + 0x1c20, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x8231, /* Device */ + 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x78, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - {0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0}, - {0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0}, - {0,0x50, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x3, 0}, - {0,0x58, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x4, 0}, - {0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0}, + /* 8231 ethernet */ + {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0}, + /* 8231 internal */ + {0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0}, + /* PCI slot */ + {0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0}, + {0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0}, + {0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0}, } }; diff --git a/src/mainboard/via/epia/mainboard.c b/src/mainboard/via/epia/mainboard.c index 303411e53f..f2ad7fdfc6 100644 --- a/src/mainboard/via/epia/mainboard.c +++ b/src/mainboard/via/epia/mainboard.c @@ -5,58 +5,57 @@ #include -void pci_routing_fixup(void) +static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 }; +static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 }; +static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 }; + +/* + Our IDSEL mappings are as follows + PCI slot is AD31 (device 15) (00:14.0) + Southbridge is AD28 (device 12) (00:11.0) +*/ +static void pci_routing_fixup(void) { struct pci_dev *dev; - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); if (dev != NULL) { - /* - * initialize PCI interupts - these assignments depend - * on the PCB routing of PINTA-D - */ + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D + + PINTA = IRQ11 + PINTB = IRQ5 + PINTC = IRQ10 + PINTD = IRQ12 + */ pci_write_config_byte(dev, 0x55, 0xb0); pci_write_config_byte(dev, 0x56, 0xa5); pci_write_config_byte(dev, 0x57, 0xc0); } + + // Standard southbridge components + printk_info("setting southbridge\n"); + pci_assign_irqs(0, 0x11, southbridgeIrqs); + + // Ethernet built into southbridge + printk_info("setting ethernet\n"); + pci_assign_irqs(0, 0x12, enetIrqs); + + // PCI slot + printk_info("setting pci slot\n"); + pci_assign_irqs(0, 0x14, slotIrqs); + } -void -ethernet_fixup() -{ - struct pci_dev *dev; - u8 byte; - printk_info("Ethernet fixup\n"); - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - if (dev != NULL) { - /* enable lan */ - pci_read_config_byte(dev, 0x51, &byte); - printk_debug("Get FC 2 in reg. 51 is 0x%x\n", byte); - byte |= 0x30; - printk_debug("Set FC 2 in reg. 51 to 0x%x\n", byte); - pci_write_config_byte(dev, 0x51, byte); - - /* setup interrupt */ - pci_read_config_byte(dev, 0x4d, &byte); - printk_debug("Get IRQ Control in reg. 4d is 0x%x\n", byte); - byte |= 0x20; - printk_debug("Set IRQ Control in reg. 4d to 0x%x\n", byte); - pci_write_config_byte(dev, 0x4d, byte); - - /* setup PINTA */ - pci_read_config_byte(dev, 0x55, &byte); - printk_debug("Get IRQ Control in reg. 55 is 0x%x\n", byte); - byte = 0x50; - printk_debug("Set IRQ Control in reg. 55 to 0x%x\n", byte); - pci_write_config_byte(dev, 0x55, byte); - } -} void mainboard_fixup() { printk_info("Mainboard fixup\n"); + + southbridge_fixup(); + pci_routing_fixup(); } void @@ -68,7 +67,6 @@ final_southbridge_fixup() keyboard_on(); southbridge_fixup(); pci_routing_fixup(); - ethernet_fixup(); } void diff --git a/src/southbridge/via/vt8231/ideconfig.inc b/src/southbridge/via/vt8231/ideconfig.inc new file mode 100644 index 0000000000..8c7eef2d63 --- /dev/null +++ b/src/southbridge/via/vt8231/ideconfig.inc @@ -0,0 +1,9 @@ +config_ide: +// This early setup switches IDE into compatibility mode before PCI gets +// a chance to assign I/Os + movl $CONFIG_ADDR(0, 0x89, 0x42), %eax +// movb $0x09, %dl + movb $0x00, %dl + PCI_WRITE_CONFIG_BYTE + + diff --git a/src/southbridge/via/vt8231/southbridge.c b/src/southbridge/via/vt8231/southbridge.c index 61f4340714..4cf2d8d4eb 100644 --- a/src/southbridge/via/vt8231/southbridge.c +++ b/src/southbridge/via/vt8231/southbridge.c @@ -1,101 +1,208 @@ #include #include +#include #include #include +#include -void keyboard_on() + +// #define IDE_NATIVE_MODE 1 + +void usb_on() { - volatile unsigned char regval; - struct pci_dev *dev; + unsigned char regval; - printk_debug("keyboard_on\n"); - regval = 0xcf; - - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - if (dev) { - pci_write_config_byte(dev, 0x51, regval); + /* Base 8231 controller */ + struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_8231, 0); + /* USB controller 1 */ + struct pci_dev *dev2 = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_82C586_2, 0); + /* USB controller 2 */ + struct pci_dev *dev3 = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_82C586_2, \ + dev2); +#if ENABLE_VT8231_USB + /* enable USB1 */ + if(dev2) { + pci_write_config_byte(dev2, 0x3c, 0x05); + pci_write_config_byte(dev2, 0x04, 0x07); } + if(dev0) { + pci_read_config_byte(dev0, 0x50, ®val); + regval &= ~(0x10); + pci_write_config_byte(dev0, 0x50, regval); + } + + /* enable USB2 */ + if(dev3) { + pci_write_config_byte(dev3, 0x3c, 0x05); + pci_write_config_byte(dev3, 0x04, 0x07); + } + + if(dev0) { + pci_read_config_byte(dev0, 0x50, ®val); + regval &= ~(0x20); + pci_write_config_byte(dev0, 0x50, regval); + } +#else /* disable USB1 */ - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0); - if (dev) { - pci_write_config_byte(dev, 0x3c, 0x00); - } - if (dev) { - pci_write_config_byte(dev, 0x04, 0x00); + if(dev2) { + pci_write_config_byte(dev2, 0x3c, 0x00); + pci_write_config_byte(dev2, 0x04, 0x00); } - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - if (dev) { - pci_read_config_byte(dev, 0x50, ®val); - regval |= 0x10; - pci_write_config_byte(dev, 0x50, regval); + if(dev0) { + pci_read_config_byte(dev0, 0x50, ®val); + regval |= 0x10; + pci_write_config_byte(dev0, 0x50, regval); } /* disable USB2 */ - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, \ - dev); - if (dev) { - pci_write_config_byte(dev, 0x3c, 0x00); - } - if (dev) { - pci_write_config_byte(dev, 0x04, 0x00); + if(dev3) { + pci_write_config_byte(dev3, 0x3c, 0x00); + pci_write_config_byte(dev3, 0x04, 0x00); } - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - if (dev) { - pci_read_config_byte(dev, 0x50, ®val); - regval |= 0x20; - pci_write_config_byte(dev, 0x50, regval); + if(dev0) { + pci_read_config_byte(dev0, 0x50, ®val); + regval |= 0x20; + pci_write_config_byte(dev0, 0x50, regval); } +#endif +} +void keyboard_on() +{ + unsigned char regval; + + /* Base 8231 controller */ + struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_8231, 0); + + /* kevinh/Ispiri - update entire function to use + new pci_write_config_byte */ + + if (dev0) { + pci_read_config_byte(dev0, 0x51, ®val); + regval |= 0x0f; + pci_write_config_byte(dev0, 0x51, regval); + } pc_keyboard_init(); } void nvram_on() { - /* the VIA 8231 South has a very different nvram setup than the piix4e ... */ - /* turn on ProMedia nvram. */ - /* TO DO: use the PciWriteByte function here. */ + /* + * the VIA 8231 South has a very different nvram setup than the + * piix4e ... + * turn on ProMedia nvram. + * TO DO: use the PciWriteByte function here. + */ - struct pci_dev *dev; + /* + * kevinh/Ispiri - I don't think this is the correct address/value + * intel_conf_writeb(0x80008841, 0xFF); + */ +} - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - if (dev) { - pci_write_config_byte(dev, 0x41, 0xc0); + +/* + * Enable the ethernet device and turn off stepping (because it is integrated + * inside the southbridge) + */ +void ethernet_fixup() +{ + struct pci_dev *dev, *edev; + u8 byte; + + printk_info("Ethernet fixup\n"); + + edev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0); + if (edev != NULL) { + printk_debug("Configuring VIA LAN\n"); + + /* We don't need stepping - though the device supports it */ + pci_read_config_byte(edev, PCI_COMMAND, &byte); + byte &= ~PCI_COMMAND_WAIT; + pci_write_config_byte(edev, PCI_COMMAND, byte); + } else { + printk_debug("VIA LAN not found\n"); } } + void southbridge_fixup() { unsigned char enables; - struct pci_dev *dev; - struct pci_dev *dev0; - struct pci_dev dev_cpy; - unsigned int devfn; + struct pci_dev *dev0; + struct pci_dev *dev1; + struct pci_dev *devpwr; + + // to do: use the pcibios_find function here, instead of + // hard coding the devfn. + // done - kevinh/Ispiri + + /* Base 8231 controller */ + dev0 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + /* IDE controller */ + dev1 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, \ + 0); + /* Power management controller */ + devpwr = pci_find_device(PCI_VENDOR_ID_VIA, \ + PCI_DEVICE_ID_VIA_8231_4, 0); // enable the internal I/O decode - dev0 = 0; - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - if (dev) { - dev0 = dev; - memcpy(&dev_cpy, dev, sizeof(dev_cpy)); - pci_read_config_byte(dev, 0x6c, &enables); - enables |= 0x80; - pci_write_config_byte(dev, 0x6c, enables); - } else { - printk_debug("IDE pci_find_device function 0 failed\n"); - } + enables = pci_read_config_byte(dev0, 0x6C, &enables); + enables |= 0x80; + pci_write_config_byte(dev0, 0x6C, enables); + // Map 4MB of FLASH into the address space + pci_write_config_byte(dev0, 0x41, 0x7f); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config_byte(dev0, 0x40, &enables); enables |= 0x44; + pci_write_config_byte(dev0, 0x40, enables); + + // Set 0x42 to 0xf0 to match Award bios + enables = pci_read_config_byte(dev0, 0x42, &enables); + enables |= 0xf0; + pci_write_config_byte(dev0, 0x42, enables); + + // Set bit 3 of 0x4a, to match award (dummy pci request) + enables = pci_read_config_byte(dev0, 0x4a, &enables); + enables |= 0x08; + pci_write_config_byte(dev0, 0x4a, enables); + + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) + enables = pci_read_config_byte(dev0, 0x4f, &enables); + enables |= 0x08; + pci_write_config_byte(dev0, 0x4f, enables); + + // Set 0x58 to 0x03 to match Award + pci_write_config_byte(dev0, 0x58, 0x03); + + // enable the ethernet/RTC + if(dev0) { + pci_read_config_byte(dev0, 0x51, &enables); + enables |= 0x18; + pci_write_config_byte(dev0, 0x51, enables); + } + #ifndef DISABLE_SOUTHBRIDGE_COM_PORTS // enable com1 and com2. - enables = 0x80 | 0x1 | 0x8 ; - if (dev) { - pci_write_config_byte(dev, 0x6e, enables); - } - // note: this is also a redo of some port of assembly, but we - // want everything up. + enables = pci_read_config_byte(dev0, 0x6e, &enables); + // 0x80 is enable com port b, 0x10 is to make it com2, 0x8 is enable com port a as com1 + // kevinh/Ispiri - Old code thought 0x01 would make it com1, that was + // wrong + enables = 0x80 | 0x10 | 0x8 ; + pci_write_config_byte(dev0, 0x6e, enables); + // note: this is also a redo of some port of assembly, but we want everything up. + // set com1 to 115 kbaud // not clear how to do this yet. // forget it; done in assembly. @@ -104,81 +211,131 @@ void southbridge_fixup() // enable IDE, since Linux won't do it. // First do some more things to devfn (17,0) // note: this should already be cleared, according to the book. - if (dev) { - pci_read_config_byte(dev, 0x50, &enables); - printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); - enables &= ~8; // need manifest constant here! - printk_debug("set IDE reg. 50 to 0x%x\n", enables); - pci_write_config_byte(dev, 0x50, enables); - } + pci_read_config_byte(dev0, 0x50, &enables); + printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); + enables &= ~8; // need manifest constant here! + printk_debug("set IDE reg. 50 to 0x%x\n", enables); + pci_write_config_byte(dev0, 0x50, enables); // set default interrupt values (IDE) - if (dev) { - pci_read_config_byte(dev, 0x4c, &enables); - printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); - // clear out whatever was there. - enables &= ~0xf; - enables |= 4; - printk_debug("setting reg. 4c to 0x%x\n", enables); - pci_write_config_byte(dev, 0x4c, enables); - } - + pci_read_config_byte(dev0, 0x4c, &enables); + printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); + // clear out whatever was there. + enables &= ~0xf; + enables |= 4; + printk_debug("setting reg. 4c to 0x%x\n", enables); + pci_write_config_byte(dev0, 0x4c, enables); + // set up the serial port interrupts. // com2 to 3, com1 to 4 - if (dev) { - pci_write_config_byte(dev, 0x46, 0x04); - pci_write_config_byte(dev, 0x47, 0x03); - } + pci_write_config_byte(dev0, 0x46, 0x04); + pci_write_config_byte(dev0, 0x47, 0x03); - dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0); - if (!dev) { - if (dev0) { - dev = &dev_cpy; - dev_cpy.devfn |= 1; - } - } - if (!dev) { - printk_debug("IDE pci_find_device function 1 failed\n"); - } else { - pci_read_config_byte(dev, 0x40, &enables); - printk_debug("enables in reg 0x40 0x%x\n", enables); - enables |= 3; - pci_write_config_byte(dev, 0x40, enables); + // + // Power management setup + // + // Set ACPI base address to IO 0x4000 + pci_write_config_dword(devpwr, 0x48, 0x4001); - pci_read_config_byte(dev, 0x40, &enables); - printk_debug("enables in reg 0x40 read back as 0x%x\n", \ - enables); - } + // Enable ACPI access (and setup like award) + pci_write_config_byte(devpwr, 0x41, 0x84); + + // Set hardware monitor base address to IO 0x6000 + pci_write_config_dword(devpwr, 0x70, 0x6001); + + // Enable hardware monitor (and setup like award) + pci_write_config_byte(devpwr, 0x74, 0x01); + + // set IO base address to 0x5000 + pci_write_config_dword(devpwr, 0x90, 0x5001); + + // Enable SMBus + pci_write_config_byte(devpwr, 0xd2, 0x01); + + // + // IDE setup + // +#ifndef ENABLE_IDE_NATIVE_MODE + // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI + // interrupts. Using PCI ints confuses linux for some reason. + + pci_read_config_byte(dev1, 0x42, &enables); + printk_debug("enables in reg 0x42 0x%x\n", enables); + enables &= ~0xc0; // compatability mode + pci_write_config_byte(dev1, 0x42, enables); + pci_read_config_byte(dev1, 0x42, &enables); + printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); +#endif + + pci_read_config_byte(dev1, 0x40, &enables); + printk_debug("enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pci_write_config_byte(dev1, 0x40, enables); + pci_read_config_byte(dev1, 0x40, &enables); + printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); + + // Enable prefetch buffers + pci_read_config_byte(dev1, 0x41, &enables); + enables |= 0xf0; + pci_write_config_byte(dev1, 0x41, enables); + + // Lower thresholds (cause award does it) + pci_read_config_byte(dev1, 0x43, &enables); + enables &= ~0x0f; + enables |= 0x05; + pci_write_config_byte(dev1, 0x43, enables); + + // PIO read prefetch counter (cause award does it) + pci_write_config_byte(dev1, 0x44, 0x18); + + // Use memory read multiple + pci_write_config_byte(dev1, 0x45, 0x1c); // address decoding. // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - if (dev) { - pci_read_config_byte(dev, 0x9, &enables); - printk_debug("enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. - enables &= ~0xf; - // cf/cg silicon needs an 'f' here. - enables |= 0xf; - pci_write_config_byte(dev, 0x9, enables); - pci_read_config_byte(dev, 0x9, &enables); - printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); + // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // used in native mode - I've changed back to classic + pci_read_config_byte(dev1, 0x9, &enables); + printk_debug("enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. +#if ENABLE_IDE_NATIVE_MODE + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; +#else + enables &= ~0x5; +#endif - // standard bios sets master bit. - pci_read_config_byte(dev, 0x4, &enables); - printk_debug("command in reg 0x4 0x%x\n", enables); - enables |= 5; - pci_write_config_byte(dev, 0x4, enables); - pci_read_config_byte(dev, 0x4, &enables); - printk_debug("command in reg 0x4 reads back as 0x%x\n", \ - enables); - // oh well, the PCI BARs don't work right. - // This chip will not work unless IDE runs at standard legacy - // values. + pci_write_config_byte(dev1, 0x9, enables); + pci_read_config_byte(dev1, 0x9, &enables); + printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); - pci_write_config_dword(dev, 0x10, 0x1f1); - pci_write_config_dword(dev, 0x14, 0x3f5); - pci_write_config_dword(dev, 0x18, 0x171); - pci_write_config_dword(dev, 0x1c, 0x375); - pci_write_config_dword(dev, 0x20, 0xcc0); - } + // standard bios sets master bit. + pci_read_config_byte(dev1, 0x4, &enables); + printk_debug("command in reg 0x4 0x%x\n", enables); + enables |= 7; + + // No need for stepping - kevinh@ispiri.com + enables &= ~0x80; + + pci_write_config_byte(dev1, 0x4, enables); + pci_read_config_byte(dev1, 0x4, &enables); + printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); + +#if (!ENABLE_IDE_NATIVE_MODE) + // Use compatability mode - per award bios + pci_write_config_dword(dev1, 0x10, 0x0); + pci_write_config_dword(dev1, 0x14, 0x0); + pci_write_config_dword(dev1, 0x18, 0x0); + pci_write_config_dword(dev1, 0x1c, 0x0); + + // Force interrupts to use compat mode - just like Award bios + pci_write_config_byte(dev1, 0x3d, 00); + pci_write_config_byte(dev1, 0x3c, 0xff); +#endif + + ethernet_fixup(); + + // Start the rtc + rtc_init(0); } diff --git a/src/superio/via/vt8231/setup_ethernet.inc b/src/superio/via/vt8231/setup_ethernet.inc index 7583c0c639..717e0a6bfd 100644 --- a/src/superio/via/vt8231/setup_ethernet.inc +++ b/src/superio/via/vt8231/setup_ethernet.inc @@ -2,10 +2,13 @@ * This early setup is a handy place to enable the Ethernet if the user wants * it. */ -#if ENABLE_VT8231_LAN enable_eth: - movl CONFIG_ADDR(0, SUPERIO_DEVFN, 0x51), %eax - movb $0x10, %dl - PCI_WRITE_CONFIG_BYTE -#endif + movl CONFIG_ADDR(0, SUPERIO_DEVFN, 0x50), %eax + PCI_READ_CONFIG_DWORD + /* Turn on just the Ethernet */ + orl $0x1000, %eax + mov %eax, %ecx + + movl $CONFIG_ADDR(0, SUPERIO_DEVFN, 0x50), %eax + PCI_WRITE_CONFIG_DWORD