From 26d6da453394977c186060a6dd9ea4463279122a Mon Sep 17 00:00:00 2001 From: Kun-Yi Chen Date: Thu, 26 Jun 2025 00:09:37 +0800 Subject: [PATCH] mb/lattepanda/mu: Correct UART1 pinmux for native mode Correct UART1 TX/RX pad configuration in early_gpio.c from NF2 to NF1. This enables proper UART1 signaling on GPP_D17 and GPP_D18 when operating in native mode. This change is based on guidance from Intel Doc. No. 648094. TEST=Patched and booted board. Confirmed UART1 communication works via serial adapter. Loopback test passed. Change-Id: Ib1f5ee17e6f3d8a845d024e6b8593606b0430b6f Signed-off-by: Kun-Yi Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/88195 Reviewed-by: Matt DeVillier Reviewed-by: Felix Singer Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/lattepanda/mu/early_gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lattepanda/mu/early_gpio.c b/src/mainboard/lattepanda/mu/early_gpio.c index f44e67dcfb..e08e7bbd55 100644 --- a/src/mainboard/lattepanda/mu/early_gpio.c +++ b/src/mainboard/lattepanda/mu/early_gpio.c @@ -10,9 +10,9 @@ static const struct pad_config early_uart_gpio_table[] = { /* UART0 TX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART1 RX */ - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* UART1 TX */ - PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* UART2 RX */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF2), /* UART2 TX */