From 26d494b57a1450efa4d21cc5884435770e465ee9 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Fri, 28 Feb 2025 17:11:07 +0530 Subject: [PATCH] mb/google/brya/gladios: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on gladios and verify that the device suspends to S0ix. Change-Id: I329e3a99e2e5c7cf4a51d7d8606987f5277d4584 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/86648 Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/gladios/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb index 4c3fffff6f..6c3eaf952a 100644 --- a/src/mainboard/google/brya/variants/gladios/overridetree.cb +++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb @@ -149,6 +149,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe STORAGE STORAGE_NVME end #NVMe device ref tbt_pcie_rp0 off end