From 261274992d03a41c75819c1e7b24bdbb5e4eba7a Mon Sep 17 00:00:00 2001 From: Alicja Michalska Date: Thu, 22 Jan 2026 02:03:56 +0100 Subject: [PATCH] soc/intel/pantherlake: Enable all RootPorts on PTL-H484 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to EDS #872188, PTL-H484 has 8 more PCIe lanes than PTL-H404 and 12Xe SKUs. I believe there's been a mixup during bringup, as PCIe ACPI tables are "gated" for an SKU with more PCIe 5.0 lanes. To be exact, in a file: "src/soc/intel/pantherlake/acpi/ptl_pcie.asl" we can notice PCIe 5.0 RootPorts depending on SOC_INTEL_PANTHERLAKE_H. Google/Fatcat boards seem to be using PANTHERLAKE_U_H instead. TEST: Build/boot intel/pantherlake_crb. Make sure Linux doesn't report PCIe routing errors. Change-Id: I1d136cf1959a3851d0ac37b256fd4df28a8d30df Signed-off-by: Alicja Michalska Reviewed-on: https://review.coreboot.org/c/coreboot/+/90863 Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N Reviewed-by: Jérémy Compostella --- src/soc/intel/pantherlake/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 59369a6a46..45a8c8376e 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -253,8 +253,8 @@ config MAX_TBT_ROOT_PORTS config MAX_ROOT_PORTS int default 6 if SOC_INTEL_WILDCATLAKE - default 10 if SOC_INTEL_PANTHERLAKE_H - default 12 + default 12 if SOC_INTEL_PANTHERLAKE_H + default 10 config MAX_PCIE_CLOCK_SRC int