Initial checkin of alpha code
This commit is contained in:
Steven James
parent
a31c76090b
commit
258ccbd054
9 changed files with 1048 additions and 0 deletions
288
src/mainboard/tyan/TigerMPX/Config
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288
src/mainboard/tyan/TigerMPX/Config
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript cpu/i386/entry16.lds
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ldscript cpu/i386/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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mainboardinit cpu/i386/reset16.inc USE_FALLBACK_IMAGE
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ldscript cpu/i386/reset16.lds USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset32.inc USE_NORMAL_IMAGE
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ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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#mainboardinit northbridge/amd/amd76x/reset_test.inc
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#mainboardinit arch/i386/lib/noop_failover.inc
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#mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE
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#mainboardinit southbridge/amd/amd768/cmos_reset_failover.inc USE_FALLBACK_IMAGE
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#ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE
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ldscript arch/i386/lib/failover-noz.lds USE_FALLBACK_IMAGE
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##
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## We aren't a reset so shutdown the second cpu if present.
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##
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##
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## Setup our mtrrs
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##
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mainboardinit cpu/k7/earlymtrr.inc
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##
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## Initialize the processor busses
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##
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mainboardinit northbridge/amd/amd76x/mpinit.inc USE_FALLBACK_IMAGE
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##
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## Only the bootstrap cpu makes it here.
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## Failover if we need to
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##
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#comment out 4 debug SMJ
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#mainboardinit southbridge/amd/amd768/cmos_boot_failover.inc USE_FALLBACK_IMAGE
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## When debugging disable the watchdog timer
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##
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option MAXIMUM_CONSOLE_LOGLEVEL=7
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expr DISABLE_WATCHDOG= MAXIMUM_CONSOLE_LOGLEVEL >= 8
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mainboardinit southbridge/amd/amd768/disable_watchdog.inc DISABLE_WATCHDOG
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##
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## Setup the serial port
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##
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mainboardinit superio/winbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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##
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## Setup RAM
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##
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#mainboardinit ram/ramtest.inc
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#mainboardinit mainboard/tyan/TigerMPX/do_ramtest.inc
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mainboardinit southbridge/amd/amd768/smbus.inc
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#mainboardinit sdram/generic_dump_spd.inc
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mainboardinit mainboard/tyan/TigerMPX/mainboard_raminit.inc
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# debugging SMJ
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mainboardinit mainboard/tyan/TigerMPX/dumpdev.inc
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mainboardinit mainboard/tyan/TigerMPX/preram.inc
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##
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## Include the secondary Configuration files
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##
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northbridge amd/amd76x
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southbridge amd/amd768
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#mainboardinit arch/i386/smp/secondary.inc
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nsuperio winbond/w83627hf com1={1} com2={0} floppy=1 lpt=1 keyboard=1
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dir ../../../pc80
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dir /src/superio/winbond/w83627hf
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cpu p5
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cpu p6
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cpu k7
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##
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## Build the objects we have code for in this directory.
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##
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object mainboard.o
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object mptable.o HAVE_MP_TABLE
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#object irq_tables.o HAVE_PIRQ_TABLE
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###
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### Build options
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###
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##
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## Location of the DIMM EEPROMS on the SMBUS
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## This is fixed into a narrow range by the DIMM package standard.
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##
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option SMBUS_MEM_DEVICE_START=(0xa << 3)
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option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3)
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option SMBUS_MEM_DEVICE_INC=1
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##
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## Customize our winbond superio chip for this motherboard
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##
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option SIO_BASE=0x2e
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nooption SIO_SYSTEM_CLK_INPUT
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##
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## Build code for the fallback boot
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##
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option HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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option HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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#option HAVE_PIRQ_TABLE=1
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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option HAVE_MP_TABLE=1
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##
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## Do not build special code for the keyboard
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##
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option NO_KEYBOARD=1
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##
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## Build code to export a CMOS option table
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##
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option HAVE_OPTION_TABLE=1
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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option SMP=1
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option MAX_CPUS=2
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##
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## Build code to setup a generic IOAPIC
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##
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option IOAPIC=1
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##
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## MEMORY_HOLE instructs earlymtrr.inc to
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## enable caching from 0-640KB and to disable
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## caching from 640KB-1MB using fixed MTRRs
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##
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## Enabling this option breaks SMP because secondary
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## CPU identification depends on only variable MTRRs
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## being enabled.
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##
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nooption MEMORY_HOLE
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##
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## Enable both fixed and variable MTRRS
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## When we setup MTRRs in mtrr.c
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##
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## We must setup the fixed mtrrs or we confuse SMP secondary
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## processor identification
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##
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option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
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##
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## Clean up the motherboard id strings
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##
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option MAINBOARD_PART_NUMBER=TIGER MPX
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option MAINBOARD_VENDOR=Tyan
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##
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## Let Assembly code know where on the pci bus the AMD southbridge is
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##
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option AMD766_DEV=0x3800
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##
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## Call the final_mainboard_fixup function
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##
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option FINAL_MAINBOARD_FIXUP=1
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##
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## Figure out which type of linuxBIOS image to build
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## If we aren't a fallback image we must be a normal image
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## This is useful for optional includes
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##
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option USE_FALLBACK_IMAGE=0
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expr BUILD_NORMAL_IMAGE=!USE_FALLBACK_IMAGE
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###
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### LinuxBIOS layout values
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###
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## ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE=524288
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE=65535
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##
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## Use a small 8K stack
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##
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option STACK_SIZE=0x2000
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##
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## Use a small 8K heap
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##
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option HEAP_SIZE=0x2000
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##
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## Only use the option table in a normal image
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##
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expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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expr ROM_SECTION_SIZE =(USE_FALLBACK_IMAGE*65536)+(BUILD_NORMAL_IMAGE*(ROM_SIZE - 65536))
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expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(BUILD_NORMAL_IMAGE*0)
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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#expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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expr ZKERNEL_START = 0xfff80000 + (0x10000 * BUILD_NORMAL_IMAGE)
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expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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#expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE
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expr _ROMBASE = 0xffff0000 - ( 0x10000 * BUILD_NORMAL_IMAGE)
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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#expr XIP_ROM_SIZE = 65536
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#expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
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#option XIP_ROM_SIZE=65536
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#option XIP_ROM_BASE=0xffff0000
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# XIP_ROM_SIZE && XIP_ROM_BASE values that work.
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#option XIP_ROM_SIZE=0x8000
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#option XIP_ROM_BASE=0xffff8000
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##
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## Compute where the SMP startup code needs to live
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## FIXME I don't see how to make this work for the normal image....
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##
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option START_CPU_SEG=0xf0000
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27
src/mainboard/tyan/TigerMPX/STATUS
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27
src/mainboard/tyan/TigerMPX/STATUS
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@ -0,0 +1,27 @@
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# These are keyword-value pairs.
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# a : separates the keyword from the value
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# the value is arbitrary text delimited by newline.
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# continuation, if needed, will be via the \ at the end of a line
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# comments are indicated by a '#' as the first character.
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# the keywords are case-INSENSITIVE
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owner: Steven James
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email: pyro@linuxlabs.com
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#status: One of unsupported, unstable, stable
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status: unstable
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explanation: just entering alpha primary/fallback config not tested
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flash-types:
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payload-types: ELF, etherboot, bootselect
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# e.g. linux, plan 9, wince, etc.
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OS-types: linux
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# e.g. "Plan 9 interrupts don't work on this chipset"
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OS-issues:
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console-types: serial
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# vga is unsupported, unstable, or stable
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vga: unsupported
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# Last-known-good follows the internationl date standard: day/month/year
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last-known-good: 10/01/2003
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Comments:
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Links:
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Mainboard-revision:
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# What other mainboards are like this one? List them here.
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AKA: Tyan ThunderK7X ?
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63
src/mainboard/tyan/TigerMPX/cmos.layout
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63
src/mainboard/tyan/TigerMPX/cmos.layout
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 3 e 5 baud_rate
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392 4 e 6 debug_level
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396 1 e 1 power_on_after_fail
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#401 1 e 1 ECC_memory
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#402 1 e 2 hda_disk
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#403 1 e 2 hdb_disk
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#404 1 e 2 hdc_disk
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#405 1 e 2 hdd_disk
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#406 2 e 7 boot_device
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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#2 0 No
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#2 1 Yes
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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#7 0 Network
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#7 1 HDD
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#7 2 Floppy
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#7 3 ROM
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28
src/mainboard/tyan/TigerMPX/do_ramtest.inc
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28
src/mainboard/tyan/TigerMPX/do_ramtest.inc
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#if 0
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movl $0x000f0000, %eax
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movl $0x000f1000, %ebx
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CALLSP(ramtest)
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#endif
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#if 1
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movl $0x00100000, %eax
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movl $0x00180000, %ebx
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CALLSP(ramtest)
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xorl %eax, %eax
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movl $0x00080000, %ebx
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CALLSP(ramtest)
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#endif
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#if 1
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xorl %eax, %eax
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movl $0x00001000, %ebx
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CALLSP(ramtest)
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#endif
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#if 0
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movl $0xffe00000, %eax
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movl $0xfff00000, %ebx
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CALLSP(ramtest)
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#endif
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64
src/mainboard/tyan/TigerMPX/dumpdev.inc
Normal file
64
src/mainboard/tyan/TigerMPX/dumpdev.inc
Normal file
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/* Dump the first 64 longs for devfn 0, bus 0
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* i.e. the north bridge.
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*/
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#define CS_WRITE_BYTE(addr, byte) \
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movl $addr, %eax ; \
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movl $byte, %edx ; \
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PCI_WRITE_CONFIG_BYTE
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#define CS_WRITE_WORD(addr, word) \
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movl $addr, %eax ; \
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movl $word, %ecx ; \
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PCI_WRITE_CONFIG_WORD
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#define CS_WRITE_LONG(addr, dword) \
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movl $addr, %eax ; \
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movl $dword, %ecx ; \
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PCI_WRITE_CONFIG_DWORD
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#define DEVFN(device, function) (((device) << 3) + (function))
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#ifndef CONFIG_ADDR
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#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
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#endif
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jmp dumpdev_skip
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dd_banner: .string "dump device: "
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dd_ret: .string "\r\n"
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dd_done: .string "Done.\r\n"
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dd_before: .string "Before setting values: \r\n"
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dd_after: .string "After setting values: \r\n"
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# expects device devfn in %ecx
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dumpdev:
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mov %esp, %ebp
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CONSOLE_INFO_TX_STRING($dd_banner)
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CONSOLE_INFO_TX_HEX32(%ecx)
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CONSOLE_INFO_TX_STRING($dd_ret)
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# xorl %ecx, %ecx
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1:
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CONSOLE_INFO_TX_HEX8(%cl)
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CONSOLE_INFO_TX_CHAR($':')
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CONSOLE_INFO_TX_CHAR($' ')
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2:
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movl %ecx, %eax
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PCI_READ_CONFIG_BYTE
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CONSOLE_INFO_TX_HEX8(%al)
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CONSOLE_INFO_TX_CHAR($' ')
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incl %ecx
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testb $0xf, %cl
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jnz 2b
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CONSOLE_INFO_TX_STRING($dd_ret)
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# CONSOLE_INFO_TX_CHAR($'\r')
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# CONSOLE_INFO_TX_CHAR($'\n')
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cmpb $0, %cl
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jne 1b
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CONSOLE_INFO_TX_STRING($dd_done)
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mov %ebp, %esp
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RETSP
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dumpdev_skip:
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230
src/mainboard/tyan/TigerMPX/mainboard.c
Normal file
230
src/mainboard/tyan/TigerMPX/mainboard.c
Normal file
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#include <pci_ids.h>
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#include <pci.h>
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#include <arch/io.h>
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#include <printk.h>
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#include <delay.h>
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#include <part/mainboard.h>
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#include <part/hard_reset.h>
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#include <arch/smp/mpspec.h>
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#include <pc80/mc146818rtc.h>
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||||
#include <pc80/isa_dma.h>
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#include <superio/w83627hf.h>
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#include <superio/generic.h>
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#include <southbridge/amd/amd766.h>
|
||||
#include <northbridge/amd/amd76x.h>
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
{
|
||||
0, 1
|
||||
};
|
||||
|
||||
static void lpc_routing_fixup(void)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7440,0);
|
||||
if (dev != NULL) {
|
||||
#if 0
|
||||
/* Send ACPI, keyboard controller,
|
||||
* FDC2, FDC1, ECP
|
||||
* to the LPC bus
|
||||
*/
|
||||
pci_write_config_byte(dev, 0x51, (1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<3)|(1));
|
||||
#else
|
||||
/* Send keyboard controller,
|
||||
* FDC1, ECP
|
||||
* to the LPC bus
|
||||
* Send APCI ports 0x62 & 0x66 to the ISA bus
|
||||
*/
|
||||
pci_write_config_byte(dev, 0x51, (0<<7)|(1<<6)|(0<<5)|(1<<4)|(0<<3)|(1));
|
||||
#endif
|
||||
/* Route io for both serial ports to the LPC bus */
|
||||
pci_write_config_byte(dev, 0x52, (1<<7)|(1<<4)|(1<<3)|(0<<0));
|
||||
/* Don't route any audio ports to the LPC bus */
|
||||
pci_write_config_byte(dev, 0x53, (0<<6)|(0<<4)|(0<<3)|(0<<2)|(0<<0));
|
||||
/* Route superio configuration accesses to the LPC bus */
|
||||
pci_write_config_byte(dev, 0x54, (0<<5)|(1<<4)|(0<<2)|(0<<0));
|
||||
/* Don't use LPC decode register 4 */
|
||||
pci_write_config_byte(dev, 0x55, (0<<4)|(0<<0));
|
||||
/* Don't use LPC decode register 5 */
|
||||
pci_write_config_byte(dev, 0x56, (0<<4)|(0<<0));
|
||||
/* Route 512 byte io address range 0x0c00 - 0xc200 the LPC bus */
|
||||
pci_write_config_dword(dev, 0x58, 0x00000c01);
|
||||
/* Route 1MB memory address range 0 - 0 to the LPC bus */
|
||||
pci_write_config_dword(dev, 0x5c, 0x00000000);
|
||||
|
||||
} else
|
||||
printk_alert("Count not locate ISA bridge\n");
|
||||
}
|
||||
|
||||
|
||||
static void enable_reset_port_0xcf9(void)
|
||||
{
|
||||
/* FIXME this code is correct but the bit isn't getting set on my test machine. */
|
||||
struct pci_dev *dev;
|
||||
dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7443, 0);
|
||||
if (dev != NULL) {
|
||||
unsigned char byte;
|
||||
/* Enable reset port 0xcf9 */
|
||||
pci_read_config_byte(dev, 0x41, &byte);
|
||||
pci_write_config_byte(dev, 0x41, byte | (1<<5));
|
||||
} else
|
||||
printk_alert("mainboard fixup: could not locate ACPI bridge\n");
|
||||
}
|
||||
|
||||
|
||||
static void print_whami(void)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
u32 whami;
|
||||
/* Find out which processor I'm running on, and if it was the boot
|
||||
* procesor so I can verify everything was setup correctly
|
||||
*/
|
||||
dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C,0);
|
||||
if (dev != NULL) {
|
||||
pci_read_config_dword(dev, 0x80, &whami);
|
||||
printk_spew("whami = 0x%08lx\n", whami);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void fixup_adaptec_7899P(struct pci_dev *pdev)
|
||||
{
|
||||
/* Enable writes to the device id */
|
||||
pci_write_config_byte(pdev, 0xff, 1);
|
||||
/* Set the device id */
|
||||
pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_ADAPTEC2_7899P);
|
||||
/* Set the subsytem vendor id */
|
||||
// pci_write_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN);
|
||||
pci_write_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, 0x10f1);
|
||||
/* Set the subsytem id */
|
||||
pci_write_config_word(pdev, PCI_SUBSYSTEM_ID, 0x2462);
|
||||
/* Disable writes to the device id */
|
||||
pci_write_config_byte(pdev, 0xff, 0);
|
||||
}
|
||||
|
||||
static void onboard_scsi_fixup(void)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
|
||||
/* Set the scsi device id's */
|
||||
dev = pci_find_slot(0, PCI_DEVFN(0xd, 0));
|
||||
if (dev != NULL) {
|
||||
fixup_adaptec_7899P(dev);
|
||||
}
|
||||
/* Set the scsi device id's */
|
||||
dev = pci_find_slot(0, PCI_DEVFN(0xd, 1));
|
||||
if (dev != NULL) {
|
||||
fixup_adaptec_7899P(dev);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#define MAINBOARD_POWER_OFF 0
|
||||
#define MAINBOARD_POWER_ON 1
|
||||
|
||||
#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#endif
|
||||
|
||||
static void set_power_on_after_power_fail(int setting)
|
||||
{
|
||||
switch(setting) {
|
||||
case MAINBOARD_POWER_ON:
|
||||
default:
|
||||
amd766_power_after_power_fail(1);
|
||||
w83627hf_power_after_power_fail(POWER_ON);
|
||||
break;
|
||||
case MAINBOARD_POWER_OFF:
|
||||
amd766_power_after_power_fail(0);
|
||||
w83627hf_power_after_power_fail(POWER_OFF);
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void setup_pci_irq_to_isa_routing(void)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7443, 0);
|
||||
if (dev != NULL) {
|
||||
/*
|
||||
* PIRQA -> 5
|
||||
* PIRQB -> 10
|
||||
* PIRQC -> 11
|
||||
* PIRQD -> 3
|
||||
*/
|
||||
pci_write_config_word(dev, 0x56,(3 << 12)|(0xb << 8)|(0xa <<4)|(5 <<0));
|
||||
}
|
||||
}
|
||||
|
||||
static void hide_devices(void)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, 0);
|
||||
if (dev) {
|
||||
u8 byte;
|
||||
pci_read_config_byte(dev, 0x48, &byte);
|
||||
#if 0
|
||||
/* Hide both the ide controller and the usb controller */
|
||||
pci_write_config_byte(dev, 0x48, byte | (0<<3)|(1<<2)|(1<<1));
|
||||
#endif
|
||||
#if 0
|
||||
/* Hide the usb controller */
|
||||
pci_write_config_byte(dev, 0x48, byte | (0<<3)|(1<<2)|(0<<1));
|
||||
#endif
|
||||
#if 1
|
||||
/* Hide no devices */
|
||||
pci_write_config_byte(dev, 0x48, byte | (0<<3)|(0<<2)|(0<<1));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_fixup(void)
|
||||
{
|
||||
int power_on_after_power_fail;
|
||||
|
||||
amd766_disable_watchdog();
|
||||
lpc_routing_fixup();
|
||||
amd766_enable_ioapic();
|
||||
amd766_enable_serial_irqs(1, 0, 0);
|
||||
enable_reset_port_0xcf9();
|
||||
amd766_enable_port92_reset();
|
||||
#if 0
|
||||
print_whami();
|
||||
#endif
|
||||
amd766_enable_ide(1,1);
|
||||
onboard_scsi_fixup();
|
||||
amd766_cpu_reset_sends_init();
|
||||
rtc_init(0);
|
||||
amd766_decode_stop_grant(DECODE_STPGNT_DATA);
|
||||
amd766_posted_memory_write_enable();
|
||||
amd766_set_pm_classcode();
|
||||
amd766_mouse_sends_irq12();
|
||||
setup_pci_irq_to_isa_routing();
|
||||
amd76x_setup_pci_arbiter();
|
||||
isa_dma_init();
|
||||
|
||||
power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
get_option(&power_on_after_power_fail, "power_on_after_fail");
|
||||
set_power_on_after_power_fail(power_on_after_power_fail);
|
||||
#if 0
|
||||
amd766_usb_setup();
|
||||
#endif
|
||||
#if 0
|
||||
hide_devices();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void final_mainboard_fixup(void)
|
||||
{
|
||||
#if 0
|
||||
enable_ide_devices();
|
||||
#endif
|
||||
}
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
amd766_hard_reset();
|
||||
}
|
||||
140
src/mainboard/tyan/TigerMPX/mainboard_raminit.inc
Normal file
140
src/mainboard/tyan/TigerMPX/mainboard_raminit.inc
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
jmp mainboard_raminit_out
|
||||
#define DEFAULT_RAM_TRACE_SETTINGS 0
|
||||
#define USE_ECC_SDRAM 1
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Routine: spd_to_dimm_side0
|
||||
* Arguments: %bl SMBUS_MEM_DEVICE
|
||||
*
|
||||
* Results: %edx DIMM register index
|
||||
*
|
||||
* Used: %ebx, %edx, %esp
|
||||
* Trashed: %eflags
|
||||
* Preserved: %eax, %ebx, %ecx, %esi, %edi, %ebp
|
||||
*
|
||||
* Effects: Dimms are not necessarily in the same order on the smbus
|
||||
* as they are in chipset register indexes. This function
|
||||
* maps the SMBUS device id to the logical index in
|
||||
* the chipset, that is used to refer to a particular dimm.
|
||||
*/
|
||||
spd_to_dimm_side0:
|
||||
movl %ebx, %edx
|
||||
andl $0xff, %edx
|
||||
subl $(SMBUS_MEM_DEVICE_START), %edx
|
||||
/* 0 -> 0 */
|
||||
cmpl $0, %edx
|
||||
jne 1f
|
||||
movl $0, %edx
|
||||
RETSP
|
||||
/* 1 -> 6 */
|
||||
1: cmpl $1, %edx
|
||||
jne 1f
|
||||
movl $6, %edx
|
||||
RETSP
|
||||
/* 2 -> 4 */
|
||||
1: cmpl $2, %edx
|
||||
jne 1f
|
||||
movl $4, %edx
|
||||
RETSP
|
||||
/* 3 -> 2 */
|
||||
1: movl $2, %edx
|
||||
RETSP
|
||||
|
||||
|
||||
/*
|
||||
* Routine: spd_to_dimm_side1
|
||||
* Arguments: %bl SMBUS_MEM_DEVICE
|
||||
*
|
||||
* Results: %edx DIMM register index
|
||||
*
|
||||
* Used: %ebx, %edx, %esp
|
||||
* Trashed: %eflags
|
||||
* Preserved: %eax, %ebx, %ecx, %esi, %edi, %ebp
|
||||
*
|
||||
* Effects: Dimms are not necessarily in the same order on the smbus
|
||||
* as they are in chipset register indexes. This function
|
||||
* maps the SMBUS device id to the logical index in
|
||||
* the chipset, that is used to refer to a particular dimm.
|
||||
*/
|
||||
spd_to_dimm_side1:
|
||||
movl %ebx, %edx
|
||||
andl $0xff, %edx
|
||||
subl $(SMBUS_MEM_DEVICE_START), %edx
|
||||
/* 0 -> 1 */
|
||||
cmpl $0, %edx
|
||||
jne 1f
|
||||
movl $1, %edx
|
||||
RETSP
|
||||
/* 1 -> 7 */
|
||||
1: cmpl $1, %edx
|
||||
jne 1f
|
||||
movl $7, %edx
|
||||
RETSP
|
||||
/* 2 -> 5 */
|
||||
1: cmpl $2, %edx
|
||||
jne 1f
|
||||
movl $5, %edx
|
||||
RETSP
|
||||
/* 3 -> 3 */
|
||||
1: movl $3, %edx
|
||||
RETSP
|
||||
|
||||
|
||||
/* Set the calibration delay. These values may need to change per mainboard
|
||||
* so we put them here.
|
||||
*/
|
||||
|
||||
sdram_software_calibration_delay:
|
||||
#if DEFAULT_RAM_TRACE_SETTINGS
|
||||
.byte 0x69, 0x00, 0x00, 0x6b
|
||||
#else
|
||||
.byte 0x69, 0x00, 0x00, 0x54
|
||||
#endif
|
||||
|
||||
mainboard_constant_register_values:
|
||||
#if DEFAULT_RAM_TRACE_SETTINGS
|
||||
#else
|
||||
.long 0x18c, 0x090e2d0e
|
||||
.long 0x190, 0x3f0f2d0e
|
||||
.long 0x194, 0x2d0e2d0e
|
||||
.long 0x198, 0x2d0e2d0e
|
||||
#endif
|
||||
#if USE_ECC_SDRAM
|
||||
.long 0x48, (3 << 14)|(2 << 10)|(0 << 8)|(0 << 4)|(0 << 0)
|
||||
#else
|
||||
.long 0x48, 0
|
||||
#endif
|
||||
mainboard_constant_register_values_end:
|
||||
|
||||
|
||||
/*
|
||||
* Routine: mainboard_verify_dram_timing
|
||||
* Arguments: %edi the computed timing for the current dimm.
|
||||
* Trashed: %eflags
|
||||
* Results: cf clear
|
||||
* %edi has a timing supported by this motherboard
|
||||
* On Error:
|
||||
* cf set
|
||||
* %edi holds a timing not supported by this motherboard
|
||||
*
|
||||
* Effects: Verifies we can use the current dimm settings
|
||||
* on the tyan guinness motherboard.
|
||||
* Currently the only potential problem is putting
|
||||
* in unregistered SDRAM.
|
||||
*/
|
||||
mainboard_verify_dram_timing:
|
||||
testl $(1<<27), %edi
|
||||
jnz mainboard_verify_dram_timing_ok
|
||||
mainboard_verify_dram_timing_error:
|
||||
stc
|
||||
jmp mainboard_verify_dram_timing_out
|
||||
mainboard_verify_dram_timing_ok:
|
||||
clc
|
||||
mainboard_verify_dram_timing_out:
|
||||
RET_LABEL(mainboard_verify_dram_timing)
|
||||
|
||||
#undef DEFAULT_RAM_TRACE_SETTINGS
|
||||
mainboard_raminit_out:
|
||||
|
||||
192
src/mainboard/tyan/TigerMPX/mptable.c
Normal file
192
src/mainboard/tyan/TigerMPX/mptable.c
Normal file
|
|
@ -0,0 +1,192 @@
|
|||
/* generatred by MPTable, version 2.0.15*/
|
||||
/* as modified by RGM for LinuxBIOS */
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <string.h>
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "LiLa ";
|
||||
static const char productid[12] = "TigerMPX ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc, processor_map);
|
||||
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "ISA ");
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 4, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 5, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 8, 0x20, base);
|
||||
}
|
||||
}
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x5, 0x2, 0x5);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x6, 0x2, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x7, 0x2, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x9, 0x2, 0x9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x3, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xb, 0x2, 0xb);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xf, 0x2, 0xf);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x20, 0x2, 0x13);
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* MP Config Extended Table Entries:
|
||||
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: I/O address
|
||||
address base: 0x0
|
||||
address range: 0x10000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0x20000000
|
||||
address range: 0xd4400000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: prefetch address
|
||||
address base: 0xf4400000
|
||||
address range: 0x7c00000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xfc000000
|
||||
address range: 0x2e00000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xfee01000
|
||||
address range: 0x11ff000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xa0000
|
||||
address range: 0x24000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xc8000
|
||||
address range: 0x2000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xcc000
|
||||
address range: 0x2000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xd0000
|
||||
address range: 0x1000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xd2000
|
||||
address range: 0x1000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xd4000
|
||||
address range: 0x1000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xd6000
|
||||
address range: 0x1000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xd8000
|
||||
address range: 0x2000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xe0000
|
||||
address range: 0x12000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xf8000
|
||||
address range: 0x4000
|
||||
--
|
||||
Bus Heirarchy
|
||||
bus ID: 3 bus info: 0x01 parent bus ID: 0--
|
||||
Compatibility Bus Address
|
||||
bus ID: 0 address modifier: add
|
||||
predefined range: 0x00000000--
|
||||
Compatibility Bus Address
|
||||
bus ID: 0 address modifier: add
|
||||
predefined range: 0x00000001 There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||
}
|
||||
16
src/mainboard/tyan/TigerMPX/preram.inc
Normal file
16
src/mainboard/tyan/TigerMPX/preram.inc
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
|
||||
jmp preram_start
|
||||
|
||||
preram_1: .string "About to initialize ram\r\n"
|
||||
preram_d: .string "Debugging messages on\r\n"
|
||||
preram_2: .string "Ram1\r\n"
|
||||
|
||||
preram_start:
|
||||
CONSOLE_INFO_TX_STRING($preram_1);
|
||||
CONSOLE_DEBUG_TX_STRING($preram_d);
|
||||
|
||||
xorl %cx, %cx
|
||||
CALLSP(dumpdev)
|
||||
|
||||
# jmp ram_initialize
|
||||
preram_out:
|
||||
Loading…
Add table
Add a link
Reference in a new issue