diff --git a/src/mainboard/tyan/TigerMPX/Config b/src/mainboard/tyan/TigerMPX/Config new file mode 100644 index 0000000000..b27b101d19 --- /dev/null +++ b/src/mainboard/tyan/TigerMPX/Config @@ -0,0 +1,288 @@ +## +## Set all of the defaults for an x86 architecture +## +arch i386 + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/i386/entry16.inc +mainboardinit cpu/i386/entry32.inc +ldscript cpu/i386/entry16.lds +ldscript cpu/i386/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +mainboardinit cpu/i386/reset16.inc USE_FALLBACK_IMAGE +ldscript cpu/i386/reset16.lds USE_FALLBACK_IMAGE +mainboardinit cpu/i386/reset32.inc USE_NORMAL_IMAGE +ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript arch/i386/lib/id.lds + + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +#mainboardinit northbridge/amd/amd76x/reset_test.inc +#mainboardinit arch/i386/lib/noop_failover.inc + +#mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE +#mainboardinit southbridge/amd/amd768/cmos_reset_failover.inc USE_FALLBACK_IMAGE +#ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE +ldscript arch/i386/lib/failover-noz.lds USE_FALLBACK_IMAGE + +## +## We aren't a reset so shutdown the second cpu if present. +## + +## +## Setup our mtrrs +## +mainboardinit cpu/k7/earlymtrr.inc + +## +## Initialize the processor busses +## +mainboardinit northbridge/amd/amd76x/mpinit.inc USE_FALLBACK_IMAGE + +## +## Only the bootstrap cpu makes it here. +## Failover if we need to +## + +#comment out 4 debug SMJ +#mainboardinit southbridge/amd/amd768/cmos_boot_failover.inc USE_FALLBACK_IMAGE + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## When debugging disable the watchdog timer +## +option MAXIMUM_CONSOLE_LOGLEVEL=7 +expr DISABLE_WATCHDOG= MAXIMUM_CONSOLE_LOGLEVEL >= 8 +mainboardinit southbridge/amd/amd768/disable_watchdog.inc DISABLE_WATCHDOG + +## +## Setup the serial port +## +mainboardinit superio/winbond/w83627hf/setup_serial.inc +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc + + +## +## Setup RAM +## +#mainboardinit ram/ramtest.inc +#mainboardinit mainboard/tyan/TigerMPX/do_ramtest.inc +mainboardinit southbridge/amd/amd768/smbus.inc +#mainboardinit sdram/generic_dump_spd.inc +mainboardinit mainboard/tyan/TigerMPX/mainboard_raminit.inc + + +# debugging SMJ +mainboardinit mainboard/tyan/TigerMPX/dumpdev.inc +mainboardinit mainboard/tyan/TigerMPX/preram.inc + + +## +## Include the secondary Configuration files +## +northbridge amd/amd76x +southbridge amd/amd768 +#mainboardinit arch/i386/smp/secondary.inc +nsuperio winbond/w83627hf com1={1} com2={0} floppy=1 lpt=1 keyboard=1 +dir ../../../pc80 +dir /src/superio/winbond/w83627hf +cpu p5 +cpu p6 +cpu k7 + +## +## Build the objects we have code for in this directory. +## +object mainboard.o +object mptable.o HAVE_MP_TABLE +#object irq_tables.o HAVE_PIRQ_TABLE + +### +### Build options +### + +## +## Location of the DIMM EEPROMS on the SMBUS +## This is fixed into a narrow range by the DIMM package standard. +## +option SMBUS_MEM_DEVICE_START=(0xa << 3) +option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3) +option SMBUS_MEM_DEVICE_INC=1 + +## +## Customize our winbond superio chip for this motherboard +## +option SIO_BASE=0x2e +nooption SIO_SYSTEM_CLK_INPUT + +## +## Build code for the fallback boot +## +option HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +option HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +#option HAVE_PIRQ_TABLE=1 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +option HAVE_MP_TABLE=1 + +## +## Do not build special code for the keyboard +## +option NO_KEYBOARD=1 + +## +## Build code to export a CMOS option table +## +option HAVE_OPTION_TABLE=1 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +option SMP=1 +option MAX_CPUS=2 + +## +## Build code to setup a generic IOAPIC +## +option IOAPIC=1 + +## +## MEMORY_HOLE instructs earlymtrr.inc to +## enable caching from 0-640KB and to disable +## caching from 640KB-1MB using fixed MTRRs +## +## Enabling this option breaks SMP because secondary +## CPU identification depends on only variable MTRRs +## being enabled. +## +nooption MEMORY_HOLE + +## +## Enable both fixed and variable MTRRS +## When we setup MTRRs in mtrr.c +## +## We must setup the fixed mtrrs or we confuse SMP secondary +## processor identification +## +option ENABLE_FIXED_AND_VARIABLE_MTRRS=1 + +## +## Clean up the motherboard id strings +## +option MAINBOARD_PART_NUMBER=TIGER MPX +option MAINBOARD_VENDOR=Tyan + +## +## Let Assembly code know where on the pci bus the AMD southbridge is +## +option AMD766_DEV=0x3800 + +## +## Call the final_mainboard_fixup function +## +option FINAL_MAINBOARD_FIXUP=1 + +## +## Figure out which type of linuxBIOS image to build +## If we aren't a fallback image we must be a normal image +## This is useful for optional includes +## +option USE_FALLBACK_IMAGE=0 +expr BUILD_NORMAL_IMAGE=!USE_FALLBACK_IMAGE + +### +### LinuxBIOS layout values +### + +## ROM_SIZE is the size of boot ROM that this board will use. +option ROM_SIZE=524288 + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +option ROM_IMAGE_SIZE=65535 + +## +## Use a small 8K stack +## +option STACK_SIZE=0x2000 + +## +## Use a small 8K heap +## +option HEAP_SIZE=0x2000 + +## +## Only use the option table in a normal image +## +expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +expr ROM_SECTION_SIZE =(USE_FALLBACK_IMAGE*65536)+(BUILD_NORMAL_IMAGE*(ROM_SIZE - 65536)) +expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(BUILD_NORMAL_IMAGE*0) + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +#expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +expr ZKERNEL_START = 0xfff80000 + (0x10000 * BUILD_NORMAL_IMAGE) +expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +#expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE +expr _ROMBASE = 0xffff0000 - ( 0x10000 * BUILD_NORMAL_IMAGE) + + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +#expr XIP_ROM_SIZE = 65536 +#expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE +#option XIP_ROM_SIZE=65536 +#option XIP_ROM_BASE=0xffff0000 + +# XIP_ROM_SIZE && XIP_ROM_BASE values that work. +#option XIP_ROM_SIZE=0x8000 +#option XIP_ROM_BASE=0xffff8000 + +## +## Compute where the SMP startup code needs to live +## FIXME I don't see how to make this work for the normal image.... +## +option START_CPU_SEG=0xf0000 diff --git a/src/mainboard/tyan/TigerMPX/STATUS b/src/mainboard/tyan/TigerMPX/STATUS new file mode 100644 index 0000000000..041e28f788 --- /dev/null +++ b/src/mainboard/tyan/TigerMPX/STATUS @@ -0,0 +1,27 @@ +# These are keyword-value pairs. +# a : separates the keyword from the value +# the value is arbitrary text delimited by newline. +# continuation, if needed, will be via the \ at the end of a line +# comments are indicated by a '#' as the first character. +# the keywords are case-INSENSITIVE +owner: Steven James +email: pyro@linuxlabs.com +#status: One of unsupported, unstable, stable +status: unstable +explanation: just entering alpha primary/fallback config not tested +flash-types: +payload-types: ELF, etherboot, bootselect +# e.g. linux, plan 9, wince, etc. +OS-types: linux +# e.g. "Plan 9 interrupts don't work on this chipset" +OS-issues: +console-types: serial +# vga is unsupported, unstable, or stable +vga: unsupported +# Last-known-good follows the internationl date standard: day/month/year +last-known-good: 10/01/2003 +Comments: +Links: +Mainboard-revision: +# What other mainboards are like this one? List them here. +AKA: Tyan ThunderK7X ? diff --git a/src/mainboard/tyan/TigerMPX/cmos.layout b/src/mainboard/tyan/TigerMPX/cmos.layout new file mode 100644 index 0000000000..78c4f0bff3 --- /dev/null +++ b/src/mainboard/tyan/TigerMPX/cmos.layout @@ -0,0 +1,63 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 3 e 5 baud_rate +392 4 e 6 debug_level +396 1 e 1 power_on_after_fail +#401 1 e 1 ECC_memory +#402 1 e 2 hda_disk +#403 1 e 2 hdb_disk +#404 1 e 2 hdc_disk +#405 1 e 2 hdd_disk +#406 2 e 7 boot_device + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +#2 0 No +#2 1 Yes +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +#7 0 Network +#7 1 HDD +#7 2 Floppy +#7 3 ROM diff --git a/src/mainboard/tyan/TigerMPX/do_ramtest.inc b/src/mainboard/tyan/TigerMPX/do_ramtest.inc new file mode 100644 index 0000000000..35ccad56d6 --- /dev/null +++ b/src/mainboard/tyan/TigerMPX/do_ramtest.inc @@ -0,0 +1,28 @@ +#if 0 + movl $0x000f0000, %eax + movl $0x000f1000, %ebx + CALLSP(ramtest) +#endif + +#if 1 + movl $0x00100000, %eax + movl $0x00180000, %ebx + CALLSP(ramtest) + + xorl %eax, %eax + movl $0x00080000, %ebx + CALLSP(ramtest) +#endif + +#if 1 + + xorl %eax, %eax + movl $0x00001000, %ebx + CALLSP(ramtest) +#endif + +#if 0 + movl $0xffe00000, %eax + movl $0xfff00000, %ebx + CALLSP(ramtest) +#endif diff --git a/src/mainboard/tyan/TigerMPX/dumpdev.inc b/src/mainboard/tyan/TigerMPX/dumpdev.inc new file mode 100644 index 0000000000..01396ba5cc --- /dev/null +++ b/src/mainboard/tyan/TigerMPX/dumpdev.inc @@ -0,0 +1,64 @@ + /* Dump the first 64 longs for devfn 0, bus 0 + * i.e. the north bridge. + */ + +#define CS_WRITE_BYTE(addr, byte) \ + movl $addr, %eax ; \ + movl $byte, %edx ; \ + PCI_WRITE_CONFIG_BYTE + +#define CS_WRITE_WORD(addr, word) \ + movl $addr, %eax ; \ + movl $word, %ecx ; \ + PCI_WRITE_CONFIG_WORD + +#define CS_WRITE_LONG(addr, dword) \ + movl $addr, %eax ; \ + movl $dword, %ecx ; \ + PCI_WRITE_CONFIG_DWORD + +#define DEVFN(device, function) (((device) << 3) + (function)) +#ifndef CONFIG_ADDR +#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) +#endif + + jmp dumpdev_skip + +dd_banner: .string "dump device: " +dd_ret: .string "\r\n" +dd_done: .string "Done.\r\n" +dd_before: .string "Before setting values: \r\n" +dd_after: .string "After setting values: \r\n" + +# expects device devfn in %ecx + +dumpdev: + mov %esp, %ebp + CONSOLE_INFO_TX_STRING($dd_banner) + CONSOLE_INFO_TX_HEX32(%ecx) + CONSOLE_INFO_TX_STRING($dd_ret) +# xorl %ecx, %ecx +1: + CONSOLE_INFO_TX_HEX8(%cl) + CONSOLE_INFO_TX_CHAR($':') + CONSOLE_INFO_TX_CHAR($' ') + +2: + movl %ecx, %eax + PCI_READ_CONFIG_BYTE + CONSOLE_INFO_TX_HEX8(%al) + CONSOLE_INFO_TX_CHAR($' ') + + incl %ecx + testb $0xf, %cl + jnz 2b + + CONSOLE_INFO_TX_STRING($dd_ret) +# CONSOLE_INFO_TX_CHAR($'\r') +# CONSOLE_INFO_TX_CHAR($'\n') + cmpb $0, %cl + jne 1b + CONSOLE_INFO_TX_STRING($dd_done) + mov %ebp, %esp + RETSP +dumpdev_skip: diff --git a/src/mainboard/tyan/TigerMPX/mainboard.c b/src/mainboard/tyan/TigerMPX/mainboard.c new file mode 100644 index 0000000000..9f72376a1d --- /dev/null +++ b/src/mainboard/tyan/TigerMPX/mainboard.c @@ -0,0 +1,230 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +unsigned long initial_apicid[MAX_CPUS] = +{ + 0, 1 +}; + +static void lpc_routing_fixup(void) +{ + struct pci_dev *dev; + dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7440,0); + if (dev != NULL) { +#if 0 + /* Send ACPI, keyboard controller, + * FDC2, FDC1, ECP + * to the LPC bus + */ + pci_write_config_byte(dev, 0x51, (1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<3)|(1)); +#else + /* Send keyboard controller, + * FDC1, ECP + * to the LPC bus + * Send APCI ports 0x62 & 0x66 to the ISA bus + */ + pci_write_config_byte(dev, 0x51, (0<<7)|(1<<6)|(0<<5)|(1<<4)|(0<<3)|(1)); +#endif + /* Route io for both serial ports to the LPC bus */ + pci_write_config_byte(dev, 0x52, (1<<7)|(1<<4)|(1<<3)|(0<<0)); + /* Don't route any audio ports to the LPC bus */ + pci_write_config_byte(dev, 0x53, (0<<6)|(0<<4)|(0<<3)|(0<<2)|(0<<0)); + /* Route superio configuration accesses to the LPC bus */ + pci_write_config_byte(dev, 0x54, (0<<5)|(1<<4)|(0<<2)|(0<<0)); + /* Don't use LPC decode register 4 */ + pci_write_config_byte(dev, 0x55, (0<<4)|(0<<0)); + /* Don't use LPC decode register 5 */ + pci_write_config_byte(dev, 0x56, (0<<4)|(0<<0)); + /* Route 512 byte io address range 0x0c00 - 0xc200 the LPC bus */ + pci_write_config_dword(dev, 0x58, 0x00000c01); + /* Route 1MB memory address range 0 - 0 to the LPC bus */ + pci_write_config_dword(dev, 0x5c, 0x00000000); + + } else + printk_alert("Count not locate ISA bridge\n"); +} + + +static void enable_reset_port_0xcf9(void) +{ + /* FIXME this code is correct but the bit isn't getting set on my test machine. */ + struct pci_dev *dev; + dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7443, 0); + if (dev != NULL) { + unsigned char byte; + /* Enable reset port 0xcf9 */ + pci_read_config_byte(dev, 0x41, &byte); + pci_write_config_byte(dev, 0x41, byte | (1<<5)); + } else + printk_alert("mainboard fixup: could not locate ACPI bridge\n"); +} + + +static void print_whami(void) +{ + struct pci_dev *dev; + u32 whami; + /* Find out which processor I'm running on, and if it was the boot + * procesor so I can verify everything was setup correctly + */ + dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C,0); + if (dev != NULL) { + pci_read_config_dword(dev, 0x80, &whami); + printk_spew("whami = 0x%08lx\n", whami); + } +} + + + +static void fixup_adaptec_7899P(struct pci_dev *pdev) +{ + /* Enable writes to the device id */ + pci_write_config_byte(pdev, 0xff, 1); + /* Set the device id */ + pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_ADAPTEC2_7899P); + /* Set the subsytem vendor id */ +// pci_write_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN); + pci_write_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, 0x10f1); + /* Set the subsytem id */ + pci_write_config_word(pdev, PCI_SUBSYSTEM_ID, 0x2462); + /* Disable writes to the device id */ + pci_write_config_byte(pdev, 0xff, 0); +} + +static void onboard_scsi_fixup(void) +{ + struct pci_dev *dev; + + /* Set the scsi device id's */ + dev = pci_find_slot(0, PCI_DEVFN(0xd, 0)); + if (dev != NULL) { + fixup_adaptec_7899P(dev); + } + /* Set the scsi device id's */ + dev = pci_find_slot(0, PCI_DEVFN(0xd, 1)); + if (dev != NULL) { + fixup_adaptec_7899P(dev); + } +} + + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 + +#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +static void set_power_on_after_power_fail(int setting) +{ + switch(setting) { + case MAINBOARD_POWER_ON: + default: + amd766_power_after_power_fail(1); + w83627hf_power_after_power_fail(POWER_ON); + break; + case MAINBOARD_POWER_OFF: + amd766_power_after_power_fail(0); + w83627hf_power_after_power_fail(POWER_OFF); + break; + + } +} + +static void setup_pci_irq_to_isa_routing(void) +{ + struct pci_dev *dev; + dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7443, 0); + if (dev != NULL) { + /* + * PIRQA -> 5 + * PIRQB -> 10 + * PIRQC -> 11 + * PIRQD -> 3 + */ + pci_write_config_word(dev, 0x56,(3 << 12)|(0xb << 8)|(0xa <<4)|(5 <<0)); + } +} + +static void hide_devices(void) +{ + struct pci_dev *dev; + dev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, 0); + if (dev) { + u8 byte; + pci_read_config_byte(dev, 0x48, &byte); +#if 0 + /* Hide both the ide controller and the usb controller */ + pci_write_config_byte(dev, 0x48, byte | (0<<3)|(1<<2)|(1<<1)); +#endif +#if 0 + /* Hide the usb controller */ + pci_write_config_byte(dev, 0x48, byte | (0<<3)|(1<<2)|(0<<1)); +#endif +#if 1 + /* Hide no devices */ + pci_write_config_byte(dev, 0x48, byte | (0<<3)|(0<<2)|(0<<1)); +#endif + } +} + +void mainboard_fixup(void) +{ + int power_on_after_power_fail; + + amd766_disable_watchdog(); + lpc_routing_fixup(); + amd766_enable_ioapic(); + amd766_enable_serial_irqs(1, 0, 0); + enable_reset_port_0xcf9(); + amd766_enable_port92_reset(); +#if 0 + print_whami(); +#endif + amd766_enable_ide(1,1); + onboard_scsi_fixup(); + amd766_cpu_reset_sends_init(); + rtc_init(0); + amd766_decode_stop_grant(DECODE_STPGNT_DATA); + amd766_posted_memory_write_enable(); + amd766_set_pm_classcode(); + amd766_mouse_sends_irq12(); + setup_pci_irq_to_isa_routing(); + amd76x_setup_pci_arbiter(); + isa_dma_init(); + + power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&power_on_after_power_fail, "power_on_after_fail"); + set_power_on_after_power_fail(power_on_after_power_fail); +#if 0 + amd766_usb_setup(); +#endif +#if 0 + hide_devices(); +#endif +} + + +void final_mainboard_fixup(void) +{ +#if 0 + enable_ide_devices(); +#endif +} + +void hard_reset(void) +{ + amd766_hard_reset(); +} diff --git a/src/mainboard/tyan/TigerMPX/mainboard_raminit.inc b/src/mainboard/tyan/TigerMPX/mainboard_raminit.inc new file mode 100644 index 0000000000..0166b0e925 --- /dev/null +++ b/src/mainboard/tyan/TigerMPX/mainboard_raminit.inc @@ -0,0 +1,140 @@ +jmp mainboard_raminit_out +#define DEFAULT_RAM_TRACE_SETTINGS 0 +#define USE_ECC_SDRAM 1 + + + + /* + * Routine: spd_to_dimm_side0 + * Arguments: %bl SMBUS_MEM_DEVICE + * + * Results: %edx DIMM register index + * + * Used: %ebx, %edx, %esp + * Trashed: %eflags + * Preserved: %eax, %ebx, %ecx, %esi, %edi, %ebp + * + * Effects: Dimms are not necessarily in the same order on the smbus + * as they are in chipset register indexes. This function + * maps the SMBUS device id to the logical index in + * the chipset, that is used to refer to a particular dimm. + */ +spd_to_dimm_side0: + movl %ebx, %edx + andl $0xff, %edx + subl $(SMBUS_MEM_DEVICE_START), %edx + /* 0 -> 0 */ + cmpl $0, %edx + jne 1f + movl $0, %edx + RETSP + /* 1 -> 6 */ +1: cmpl $1, %edx + jne 1f + movl $6, %edx + RETSP + /* 2 -> 4 */ +1: cmpl $2, %edx + jne 1f + movl $4, %edx + RETSP + /* 3 -> 2 */ +1: movl $2, %edx + RETSP + + + /* + * Routine: spd_to_dimm_side1 + * Arguments: %bl SMBUS_MEM_DEVICE + * + * Results: %edx DIMM register index + * + * Used: %ebx, %edx, %esp + * Trashed: %eflags + * Preserved: %eax, %ebx, %ecx, %esi, %edi, %ebp + * + * Effects: Dimms are not necessarily in the same order on the smbus + * as they are in chipset register indexes. This function + * maps the SMBUS device id to the logical index in + * the chipset, that is used to refer to a particular dimm. + */ +spd_to_dimm_side1: + movl %ebx, %edx + andl $0xff, %edx + subl $(SMBUS_MEM_DEVICE_START), %edx + /* 0 -> 1 */ + cmpl $0, %edx + jne 1f + movl $1, %edx + RETSP + /* 1 -> 7 */ +1: cmpl $1, %edx + jne 1f + movl $7, %edx + RETSP + /* 2 -> 5 */ +1: cmpl $2, %edx + jne 1f + movl $5, %edx + RETSP + /* 3 -> 3 */ +1: movl $3, %edx + RETSP + + +/* Set the calibration delay. These values may need to change per mainboard + * so we put them here. + */ + +sdram_software_calibration_delay: +#if DEFAULT_RAM_TRACE_SETTINGS + .byte 0x69, 0x00, 0x00, 0x6b +#else + .byte 0x69, 0x00, 0x00, 0x54 +#endif + +mainboard_constant_register_values: +#if DEFAULT_RAM_TRACE_SETTINGS +#else + .long 0x18c, 0x090e2d0e + .long 0x190, 0x3f0f2d0e + .long 0x194, 0x2d0e2d0e + .long 0x198, 0x2d0e2d0e +#endif +#if USE_ECC_SDRAM + .long 0x48, (3 << 14)|(2 << 10)|(0 << 8)|(0 << 4)|(0 << 0) +#else + .long 0x48, 0 +#endif +mainboard_constant_register_values_end: + + + /* + * Routine: mainboard_verify_dram_timing + * Arguments: %edi the computed timing for the current dimm. + * Trashed: %eflags + * Results: cf clear + * %edi has a timing supported by this motherboard + * On Error: + * cf set + * %edi holds a timing not supported by this motherboard + * + * Effects: Verifies we can use the current dimm settings + * on the tyan guinness motherboard. + * Currently the only potential problem is putting + * in unregistered SDRAM. + */ +mainboard_verify_dram_timing: + testl $(1<<27), %edi + jnz mainboard_verify_dram_timing_ok +mainboard_verify_dram_timing_error: + stc + jmp mainboard_verify_dram_timing_out +mainboard_verify_dram_timing_ok: + clc +mainboard_verify_dram_timing_out: + RET_LABEL(mainboard_verify_dram_timing) + +#undef DEFAULT_RAM_TRACE_SETTINGS +mainboard_raminit_out: + diff --git a/src/mainboard/tyan/TigerMPX/mptable.c b/src/mainboard/tyan/TigerMPX/mptable.c new file mode 100644 index 0000000000..fc8dce139b --- /dev/null +++ b/src/mainboard/tyan/TigerMPX/mptable.c @@ -0,0 +1,192 @@ +/* generatred by MPTable, version 2.0.15*/ +/* as modified by RGM for LinuxBIOS */ +#include +#include +#include +#include +#include + +void *smp_write_config_table(void *v, unsigned long * processor_map) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LiLa "; + static const char productid[12] = "TigerMPX "; + struct mp_config_table *mc; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc, processor_map); + + +/*Bus: Bus ID Type*/ + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "PCI "); + smp_write_bus(mc, 2, "PCI "); + smp_write_bus(mc, 3, "ISA "); +/*I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + { + struct pci_dev *dev; + uint32_t base; + dev = pci_find_slot(1, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 3, 0x20, base); + } + dev = pci_find_slot(1, PCI_DEVFN(0x1c,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 4, 0x20, base); + } + dev = pci_find_slot(4, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 5, 0x20, base); + } + dev = pci_find_slot(4, PCI_DEVFN(0x1c,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 8, 0x20, base); + } + } +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# +*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x5, 0x2, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x6, 0x2, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x7, 0x2, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x9, 0x2, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x3, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xb, 0x2, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xf, 0x2, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x20, 0x2, 0x13); +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x1); +/* MP Config Extended Table Entries: + +-- +System Address Space + bus ID: 0 address type: I/O address + address base: 0x0 + address range: 0x10000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0x20000000 + address range: 0xd4400000 +-- +System Address Space + bus ID: 0 address type: prefetch address + address base: 0xf4400000 + address range: 0x7c00000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xfc000000 + address range: 0x2e00000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xfee01000 + address range: 0x11ff000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xa0000 + address range: 0x24000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xc8000 + address range: 0x2000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xcc000 + address range: 0x2000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xd0000 + address range: 0x1000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xd2000 + address range: 0x1000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xd4000 + address range: 0x1000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xd6000 + address range: 0x1000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xd8000 + address range: 0x2000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xe0000 + address range: 0x12000 +-- +System Address Space + bus ID: 0 address type: memory address + address base: 0xf8000 + address range: 0x4000 +-- +Bus Heirarchy + bus ID: 3 bus info: 0x01 parent bus ID: 0-- +Compatibility Bus Address + bus ID: 0 address modifier: add + predefined range: 0x00000000-- +Compatibility Bus Address + bus ID: 0 address modifier: add + predefined range: 0x00000001 There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v, processor_map); +} diff --git a/src/mainboard/tyan/TigerMPX/preram.inc b/src/mainboard/tyan/TigerMPX/preram.inc new file mode 100644 index 0000000000..30d4353b65 --- /dev/null +++ b/src/mainboard/tyan/TigerMPX/preram.inc @@ -0,0 +1,16 @@ + + jmp preram_start + +preram_1: .string "About to initialize ram\r\n" +preram_d: .string "Debugging messages on\r\n" +preram_2: .string "Ram1\r\n" + +preram_start: + CONSOLE_INFO_TX_STRING($preram_1); + CONSOLE_DEBUG_TX_STRING($preram_d); + + xorl %cx, %cx + CALLSP(dumpdev) + +# jmp ram_initialize +preram_out: