sb/intel/lynxpoint/acpi/xhci.asl: Guard PCH-LP methods

The `LPCL` and `LPS0` methods are specific to PCH-LP, and are not used
at all on PCH-H. To prevent accidental use and to reduce the DSDT size
on PCH-H builds, add some preprocessor guards around those methods.

For the ASRock Z97 Extreme, `build/dsdt.aml` size goes from 8538 bytes
down to 7904 bytes, a reduction of about 7%.

Change-Id: I775dcde4932f6039ba7d5673364e495837a386da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

src/southbridge/intel/lynxpoint/acpi/xhci.asl

@@ -38,6 +38,7 @@ Device (XHCI)
 		PR3M, 32,  // USB3PRM
 	}
 
+#if CONFIG(INTEL_LYNXPOINT_LP)
 	// Clear status bits
 	Method (LPCL, 0, Serialized)
 	{
@@ -181,6 +182,7 @@ Device (XHCI)
 		// Clear status bits in all ports
 		LPCL ()
 	}
+#endif
 
 	Method (_PSC, 0, NotSerialized)
 	{