From 253689aebb5b59f22d11a65182c33da5a6a24547 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Feb 2026 20:50:31 +0100 Subject: [PATCH] sb/intel/lynxpoint/acpi/xhci.asl: Guard PCH-LP methods The `LPCL` and `LPS0` methods are specific to PCH-LP, and are not used at all on PCH-H. To prevent accidental use and to reduce the DSDT size on PCH-H builds, add some preprocessor guards around those methods. For the ASRock Z97 Extreme, `build/dsdt.aml` size goes from 8538 bytes down to 7904 bytes, a reduction of about 7%. Change-Id: I775dcde4932f6039ba7d5673364e495837a386da Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/91395 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel --- src/southbridge/intel/lynxpoint/acpi/xhci.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index 9c7bb2c1ac..c38a592372 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -38,6 +38,7 @@ Device (XHCI) PR3M, 32, // USB3PRM } +#if CONFIG(INTEL_LYNXPOINT_LP) // Clear status bits Method (LPCL, 0, Serialized) { @@ -181,6 +182,7 @@ Device (XHCI) // Clear status bits in all ports LPCL () } +#endif Method (_PSC, 0, NotSerialized) {