From 24ff10d76e2b6be4d90bc2ccb2843f857178e6a1 Mon Sep 17 00:00:00 2001 From: Ana Carolina Cabral Date: Tue, 25 Mar 2025 09:14:02 -0300 Subject: [PATCH] mb/amd/crater: Enable CPPC support Enable CPPC configuration in mainboard devicetree. Change-Id: Ifbe65db23aff932ceb92861426fda9358cd655be Signed-off-by: Ana Carolina Cabral Reviewed-on: https://review.coreboot.org/c/coreboot/+/87217 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/amd/crater/devicetree_renoir.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/amd/crater/devicetree_renoir.cb b/src/mainboard/amd/crater/devicetree_renoir.cb index 16d2c7e18a..cc9ad45dd1 100644 --- a/src/mainboard/amd/crater/devicetree_renoir.cb +++ b/src/mainboard/amd/crater/devicetree_renoir.cb @@ -37,6 +37,14 @@ chip soc/amd/cezanne register "s0ix_enable" = "false" + # CPPC register configuration + register "cppc_ctrl" = "true" + register "cppc_perf_limit_max_range" = "0xFF" + register "cppc_perf_limit_min_range" = "0x00" + register "cppc_epp_max_range" = "0xFF" + register "cppc_epp_min_range" = "0x00" + + # general purpose PCIe clock output configuration register "gpp_clk_config[0]" = "GPP_CLK_ON" register "gpp_clk_config[1]" = "GPP_CLK_ON"