Changes from Eric for Alpha and other support
This commit is contained in:
Ronald G. Minnich
parent
1bb9d68a20
commit
227ca052f7
26 changed files with 1846 additions and 157 deletions
393
src/include/boot/elf.h
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393
src/include/boot/elf.h
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#ifndef ELF_H
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#define ELF_H
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/* Standard ELF types. */
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#include <stdint.h>
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#include <arch/boot/boot.h>
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/* Type for a 16-bit quantity. */
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typedef uint16_t Elf32_Half;
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typedef uint16_t Elf64_Half;
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/* Types for signed and unsigned 32-bit quantities. */
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typedef uint32_t Elf32_Word;
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typedef int32_t Elf32_Sword;
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typedef uint32_t Elf64_Word;
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typedef int32_t Elf64_Sword;
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/* Types for signed and unsigned 64-bit quantities. */
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typedef uint64_t Elf32_Xword;
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typedef int64_t Elf32_Sxword;
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typedef uint64_t Elf64_Xword;
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typedef int64_t Elf64_Sxword;
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/* Type of addresses. */
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typedef uint32_t Elf32_Addr;
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typedef uint64_t Elf64_Addr;
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/* Type of file offsets. */
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typedef uint32_t Elf32_Off;
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typedef uint64_t Elf64_Off;
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/* Type for section indices, which are 16-bit quantities. */
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typedef uint16_t Elf32_Section;
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typedef uint16_t Elf64_Section;
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/* Type of symbol indices. */
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typedef uint32_t Elf32_Symndx;
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typedef uint64_t Elf64_Symndx;
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/* The ELF file header. This appears at the start of every ELF file. */
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#define EI_NIDENT (16)
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typedef struct
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{
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unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */
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Elf32_Half e_type; /* Object file type */
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Elf32_Half e_machine; /* Architecture */
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Elf32_Word e_version; /* Object file version */
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Elf32_Addr e_entry; /* Entry point virtual address */
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Elf32_Off e_phoff; /* Program header table file offset */
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Elf32_Off e_shoff; /* Section header table file offset */
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Elf32_Word e_flags; /* Processor-specific flags */
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Elf32_Half e_ehsize; /* ELF header size in bytes */
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Elf32_Half e_phentsize; /* Program header table entry size */
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Elf32_Half e_phnum; /* Program header table entry count */
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Elf32_Half e_shentsize; /* Section header table entry size */
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Elf32_Half e_shnum; /* Section header table entry count */
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Elf32_Half e_shstrndx; /* Section header string table index */
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} Elf32_Ehdr;
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typedef struct
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{
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unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */
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Elf64_Half e_type; /* Object file type */
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Elf64_Half e_machine; /* Architecture */
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Elf64_Word e_version; /* Object file version */
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Elf64_Addr e_entry; /* Entry point virtual address */
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Elf64_Off e_phoff; /* Program header table file offset */
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Elf64_Off e_shoff; /* Section header table file offset */
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Elf64_Word e_flags; /* Processor-specific flags */
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Elf64_Half e_ehsize; /* ELF header size in bytes */
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Elf64_Half e_phentsize; /* Program header table entry size */
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Elf64_Half e_phnum; /* Program header table entry count */
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Elf64_Half e_shentsize; /* Section header table entry size */
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Elf64_Half e_shnum; /* Section header table entry count */
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Elf64_Half e_shstrndx; /* Section header string table index */
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} Elf64_Ehdr;
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/* Fields in the e_ident array. The EI_* macros are indices into the
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array. The macros under each EI_* macro are the values the byte
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may have. */
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#define EI_MAG0 0 /* File identification byte 0 index */
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#define ELFMAG0 0x7f /* Magic number byte 0 */
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#define EI_MAG1 1 /* File identification byte 1 index */
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#define ELFMAG1 'E' /* Magic number byte 1 */
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#define EI_MAG2 2 /* File identification byte 2 index */
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#define ELFMAG2 'L' /* Magic number byte 2 */
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#define EI_MAG3 3 /* File identification byte 3 index */
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#define ELFMAG3 'F' /* Magic number byte 3 */
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/* Conglomeration of the identification bytes, for easy testing as a word. */
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#define ELFMAG "\177ELF"
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#define SELFMAG 4
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#define EI_CLASS 4 /* File class byte index */
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#define ELFCLASSNONE 0 /* Invalid class */
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#define ELFCLASS32 1 /* 32-bit objects */
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#define ELFCLASS64 2 /* 64-bit objects */
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#define ELFCLASSNUM 3
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#define EI_DATA 5 /* Data encoding byte index */
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#define ELFDATANONE 0 /* Invalid data encoding */
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#define ELFDATA2LSB 1 /* 2's complement, little endian */
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#define ELFDATA2MSB 2 /* 2's complement, big endian */
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#define ELFDATANUM 3
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#define EI_VERSION 6 /* File version byte index */
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/* Value must be EV_CURRENT */
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#define EI_OSABI 7 /* OS ABI identification */
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#define ELFOSABI_SYSV 0 /* UNIX System V ABI */
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#define ELFOSABI_HPUX 1 /* HP-UX */
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#define ELFOSABI_ARM 97 /* ARM */
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#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */
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#define EI_ABIVERSION 8 /* ABI version */
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#define EI_PAD 9 /* Byte index of padding bytes */
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/* Legal values for e_type (object file type). */
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#define ET_NONE 0 /* No file type */
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#define ET_REL 1 /* Relocatable file */
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#define ET_EXEC 2 /* Executable file */
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#define ET_DYN 3 /* Shared object file */
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#define ET_CORE 4 /* Core file */
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#define ET_NUM 5 /* Number of defined types */
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#define ET_LOPROC 0xff00 /* Processor-specific */
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#define ET_HIPROC 0xffff /* Processor-specific */
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/* Legal values for e_machine (architecture). */
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#define EM_NONE 0 /* No machine */
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#define EM_M32 1 /* AT&T WE 32100 */
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#define EM_SPARC 2 /* SUN SPARC */
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#define EM_386 3 /* Intel 80386 */
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#define EM_68K 4 /* Motorola m68k family */
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#define EM_88K 5 /* Motorola m88k family */
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#define EM_486 6 /* Intel 80486 */
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#define EM_860 7 /* Intel 80860 */
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#define EM_MIPS 8 /* MIPS R3000 big-endian */
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#define EM_S370 9 /* Amdahl */
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#define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */
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#define EM_RS6000 11 /* RS6000 */
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#define EM_PARISC 15 /* HPPA */
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#define EM_nCUBE 16 /* nCUBE */
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#define EM_VPP500 17 /* Fujitsu VPP500 */
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#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */
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#define EM_960 19 /* Intel 80960 */
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#define EM_PPC 20 /* PowerPC */
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#define EM_V800 36 /* NEC V800 series */
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#define EM_FR20 37 /* Fujitsu FR20 */
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#define EM_RH32 38 /* TRW RH32 */
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#define EM_MMA 39 /* Fujitsu MMA */
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#define EM_ARM 40 /* ARM */
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#define EM_FAKE_ALPHA 41 /* Digital Alpha */
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#define EM_SH 42 /* Hitachi SH */
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#define EM_SPARCV9 43 /* SPARC v9 64-bit */
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#define EM_TRICORE 44 /* Siemens Tricore */
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#define EM_ARC 45 /* Argonaut RISC Core */
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#define EM_H8_300 46 /* Hitachi H8/300 */
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#define EM_H8_300H 47 /* Hitachi H8/300H */
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#define EM_H8S 48 /* Hitachi H8S */
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#define EM_H8_500 49 /* Hitachi H8/500 */
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#define EM_IA_64 50 /* Intel Merced */
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#define EM_MIPS_X 51 /* Stanford MIPS-X */
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#define EM_COLDFIRE 52 /* Motorola Coldfire */
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#define EM_68HC12 53 /* Motorola M68HC12 */
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#define EM_NUM 54
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/* If it is necessary to assign new unofficial EM_* values, please
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pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
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chances of collision with official or non-GNU unofficial values. */
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#define EM_ALPHA 0x9026
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/* Legal values for e_version (version). */
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#define EV_NONE 0 /* Invalid ELF version */
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#define EV_CURRENT 1 /* Current version */
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#define EV_NUM 2
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/* Program segment header. */
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typedef struct
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{
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Elf32_Word p_type; /* Segment type */
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Elf32_Off p_offset; /* Segment file offset */
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Elf32_Addr p_vaddr; /* Segment virtual address */
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Elf32_Addr p_paddr; /* Segment physical address */
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Elf32_Word p_filesz; /* Segment size in file */
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Elf32_Word p_memsz; /* Segment size in memory */
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Elf32_Word p_flags; /* Segment flags */
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Elf32_Word p_align; /* Segment alignment */
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} Elf32_Phdr;
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typedef struct
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{
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Elf64_Word p_type; /* Segment type */
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Elf64_Word p_flags; /* Segment flags */
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Elf64_Off p_offset; /* Segment file offset */
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Elf64_Addr p_vaddr; /* Segment virtual address */
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Elf64_Addr p_paddr; /* Segment physical address */
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Elf64_Xword p_filesz; /* Segment size in file */
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Elf64_Xword p_memsz; /* Segment size in memory */
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Elf64_Xword p_align; /* Segment alignment */
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} Elf64_Phdr;
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/* Legal values for p_type (segment type). */
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#define PT_NULL 0 /* Program header table entry unused */
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#define PT_LOAD 1 /* Loadable program segment */
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#define PT_DYNAMIC 2 /* Dynamic linking information */
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#define PT_INTERP 3 /* Program interpreter */
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#define PT_NOTE 4 /* Auxiliary information */
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#define PT_SHLIB 5 /* Reserved */
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#define PT_PHDR 6 /* Entry for header table itself */
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#define PT_NUM 7 /* Number of defined types. */
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#define PT_LOOS 0x60000000 /* Start of OS-specific */
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#define PT_HIOS 0x6fffffff /* End of OS-specific */
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#define PT_LOPROC 0x70000000 /* Start of processor-specific */
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#define PT_HIPROC 0x7fffffff /* End of processor-specific */
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/* Legal values for p_flags (segment flags). */
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#define PF_X (1 << 0) /* Segment is executable */
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#define PF_W (1 << 1) /* Segment is writable */
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#define PF_R (1 << 2) /* Segment is readable */
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#define PF_MASKPROC 0xf0000000 /* Processor-specific */
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/* Note section contents. Each entry in the note section begins with
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a header of a fixed form. */
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typedef struct
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{
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Elf32_Word n_namesz; /* Length of the note's name. */
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Elf32_Word n_descsz; /* Length of the note's descriptor. */
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Elf32_Word n_type; /* Type of the note. */
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} Elf32_Nhdr;
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typedef struct
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{
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Elf64_Word n_namesz; /* Length of the note's name. */
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Elf64_Word n_descsz; /* Length of the note's descriptor. */
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Elf64_Word n_type; /* Type of the note. */
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} Elf64_Nhdr;
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/* Known names of notes. */
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/* Solaris entries in the note section have this name. */
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#define ELF_NOTE_SOLARIS "SUNW Solaris"
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/* Note entries for GNU systems have this name. */
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#define ELF_NOTE_GNU "GNU"
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/* Defined types of notes for Solaris. */
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/* Value of descriptor (one word) is desired pagesize for the binary. */
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#define ELF_NOTE_PAGESIZE_HINT 1
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/* Defined note types for GNU systems. */
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/* ABI information. The descriptor consists of words:
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word 0: OS descriptor
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word 1: major version of the ABI
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word 2: minor version of the ABI
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word 3: subminor version of the ABI
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*/
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#define ELF_NOTE_ABI 1
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/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI
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note section entry. */
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#define ELF_NOTE_OS_LINUX 0
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#define ELF_NOTE_OS_GNU 1
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#define ELF_NOTE_OS_SOLARIS2 2
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/* Motorola 68k specific definitions. */
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/* Intel 80386 specific definitions. */
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/* SUN SPARC specific definitions. */
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/* Values for Elf64_Ehdr.e_flags. */
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#define EF_SPARCV9_MM 3
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#define EF_SPARCV9_TSO 0
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#define EF_SPARCV9_PSO 1
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#define EF_SPARCV9_RMO 2
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#define EF_SPARC_EXT_MASK 0xFFFF00
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#define EF_SPARC_SUN_US1 0x000200
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#define EF_SPARC_HAL_R1 0x000400
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/* MIPS R3000 specific definitions. */
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/* Legal values for e_flags field of Elf32_Ehdr. */
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#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */
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#define EF_MIPS_PIC 2 /* Contains PIC code */
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#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */
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#define EF_MIPS_XGOT 8
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#define EF_MIPS_64BIT_WHIRL 16
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#define EF_MIPS_ABI2 32
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#define EF_MIPS_ABI_ON32 64
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#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */
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/* Legal values for MIPS architecture level. */
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#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
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#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
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#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
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#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
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#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
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/* Legal values for p_type field of Elf32_Phdr. */
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#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */
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#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */
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#define PT_MIPS_OPTIONS 0x70000002
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/* Special program header types. */
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#define PF_MIPS_LOCAL 0x10000000
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/* HPPA specific definitions. */
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/* Legal values for e_flags field of Elf32_Ehdr. */
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#define EF_PARISC_TRAPNL 1 /* Trap nil pointer dereference. */
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#define EF_PARISC_EXT 2 /* Program uses arch. extensions. */
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#define EF_PARISC_ARCH 0xffff0000 /* Architecture version. */
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/* Defined values are:
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0x020b PA-RISC 1.0 big-endian
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0x0210 PA-RISC 1.1 big-endian
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0x028b PA-RISC 1.0 little-endian
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0x0290 PA-RISC 1.1 little-endian
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*/
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/* Alpha specific definitions. */
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/* Legal values for e_flags field of Elf64_Ehdr. */
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#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */
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#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */
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/* PowerPC specific declarations */
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/* ARM specific declarations */
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/* Processor specific flags for the ELF header e_flags field. */
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#define EF_ARM_RELEXEC 0x01
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#define EF_ARM_HASENTRY 0x02
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#define EF_ARM_INTERWORK 0x04
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#define EF_ARM_APCS_26 0x08
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#define EF_ARM_APCS_FLOAT 0x10
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#define EF_ARM_PIC 0x20
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#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use */
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#define EF_NEW_ABI 0x80
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#define EF_OLD_ABI 0x100
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/* ARM-specific program header flags */
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#define PF_ARM_SB 0x10000000 /* Segment contains the location
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addressed by the static base */
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#if ELF_CLASS == ELFCLASS32
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typedef Elf32_Ehdr Elf_ehdr;
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typedef Elf32_Phdr Elf_phdr;
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#endif
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#if ELF_CLASS == ELFCLASS64
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typedef Elf64_Ehdr Elf_ehdr;
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typedef Elf64_Phdr Elf_phdr;
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#endif
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extern int elf_check_arch(Elf_ehdr *ehdr);
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extern void jmp_to_elf_entry(void *entry, void *ube);
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#endif /* elf.h */
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7
src/include/kmalloc.h
Normal file
7
src/include/kmalloc.h
Normal file
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@ -0,0 +1,7 @@
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#ifndef KMALLOC_H
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#define KMALLOC_H
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#include <stdlib.h>
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#define kmalloc(x,y) malloc(x)
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#endif /* KMALLOC_H */
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@ -14,27 +14,6 @@
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* PCI System Design Guide
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*/
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#ifdef EMULATE
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// you would not BELIEVE the errors you get if you include stdio.h here
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// since we can build without including it, just SKIP IT
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#if 0
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#undef __NFDBITS
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#undef __FDMASK
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#define off_t
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#define ssize_t
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#include <stdio.h>
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#include <unistd.h> /* for libc5 */
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#endif
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extern void printf(char *format, ...);
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#define printk printf
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#define display(x) printk(x)
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#define printint(x) printf("0x%x", x)
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#endif /* EMULATE */
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#ifndef PCI_H
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#define PCI_H
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@ -59,7 +38,7 @@ extern void printf(char *format, ...);
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#define PCI_STATUS 0x06 /* 16 bits */
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#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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#define PCI_STATUS_UDF 0x40 /* Support User Definable Features */
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#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
|
||||
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
|
||||
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
|
||||
|
|
@ -107,7 +86,7 @@ extern void printf(char *format, ...);
|
|||
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
|
||||
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
|
||||
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
|
||||
|
|
@ -156,7 +135,8 @@ extern void printf(char *format, ...);
|
|||
#define PCI_PREF_LIMIT_UPPER32 0x2c
|
||||
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
|
||||
#define PCI_IO_LIMIT_UPPER16 0x32
|
||||
/* 0x34-0x3b is reserved */
|
||||
/* 0x34 same as for htype 0 */
|
||||
/* 0x35-0x3b is reserved */
|
||||
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
|
||||
/* 0x3c-0x3d are same as for htype 0 */
|
||||
#define PCI_BRIDGE_CONTROL 0x3e
|
||||
|
|
@ -169,7 +149,8 @@ extern void printf(char *format, ...);
|
|||
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
|
||||
|
||||
/* Header type 2 (CardBus bridges) */
|
||||
/* 0x14-0x15 reserved */
|
||||
#define PCI_CB_CAPABILITY_LIST 0x14
|
||||
/* 0x15 reserved */
|
||||
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
|
||||
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
|
||||
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
|
||||
|
|
@ -206,10 +187,81 @@ extern void printf(char *format, ...);
|
|||
/* 0x48-0x7f reserved */
|
||||
|
||||
/* Capability lists */
|
||||
|
||||
#define PCI_CAP_LIST_ID 0 /* Capability ID */
|
||||
#define PCI_CAP_ID_PM 0x01 /* Power Management */
|
||||
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
|
||||
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
|
||||
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
|
||||
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
|
||||
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
|
||||
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
|
||||
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
|
||||
#define PCI_CAP_SIZEOF 4
|
||||
|
||||
/* Power Management Registers */
|
||||
|
||||
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
|
||||
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
|
||||
#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
|
||||
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
|
||||
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
|
||||
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
|
||||
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
|
||||
#define PCI_PM_CTRL 4 /* PM control and status register */
|
||||
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
|
||||
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
|
||||
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
|
||||
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
|
||||
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
|
||||
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
|
||||
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
|
||||
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
|
||||
#define PCI_PM_DATA_REGISTER 7 /* (??) */
|
||||
#define PCI_PM_SIZEOF 8
|
||||
|
||||
/* AGP registers */
|
||||
|
||||
#define PCI_AGP_VERSION 2 /* BCD version number */
|
||||
#define PCI_AGP_RFU 3 /* Rest of capability flags */
|
||||
#define PCI_AGP_STATUS 4 /* Status register */
|
||||
#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
|
||||
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
|
||||
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
|
||||
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
|
||||
#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
|
||||
#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
|
||||
#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
|
||||
#define PCI_AGP_COMMAND 8 /* Control register */
|
||||
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
|
||||
#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
|
||||
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
|
||||
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
|
||||
#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
|
||||
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
|
||||
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
|
||||
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
|
||||
#define PCI_AGP_SIZEOF 12
|
||||
|
||||
/* Slot Identification */
|
||||
|
||||
#define PCI_SID_ESR 2 /* Expansion Slot Register */
|
||||
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
|
||||
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
|
||||
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
|
||||
|
||||
/* Message Signalled Interrupts registers */
|
||||
|
||||
#define PCI_MSI_FLAGS 2 /* Various flags */
|
||||
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
|
||||
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
|
||||
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
|
||||
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
|
||||
#define PCI_MSI_RFU 3 /* Rest of capability flags */
|
||||
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
|
||||
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
|
||||
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
|
||||
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
|
||||
|
||||
/*
|
||||
* The PCI interface treats multi-function devices as independent
|
||||
|
|
@ -377,8 +429,7 @@ void intel_conf_writeb(unsigned long port, unsigned char value);
|
|||
unsigned char intel_conf_readb(unsigned long port);
|
||||
|
||||
|
||||
#define kmalloc(x, y) malloc(x)
|
||||
void *malloc(unsigned int);
|
||||
#include <kmalloc.h>
|
||||
|
||||
// Rounding for boundaries.
|
||||
// Due to some chip bugs, go ahead and roung IO to 16
|
||||
|
|
|
|||
9
src/include/stdlib.h
Normal file
9
src/include/stdlib.h
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
#ifndef STDLIB_H
|
||||
#define STDLIB_H
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
extern void *malloc(size_t size);
|
||||
void free(void *ptr);
|
||||
|
||||
#endif /* STDLIB_H */
|
||||
|
|
@ -28,12 +28,13 @@ void intel_interrupts_on(void);
|
|||
void pc_keyboard_init(void);
|
||||
void intel_mainboard_fixup(void);
|
||||
unsigned long sizeram(void);
|
||||
|
||||
|
||||
#ifdef INTEL_PPRO_MTRR
|
||||
void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK);
|
||||
#endif
|
||||
|
||||
#include <pci.h>
|
||||
/* FIXME: how should we handle other architectures for pci access here ?? */
|
||||
#include <pci-i386.h>
|
||||
|
||||
#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
|
||||
|
|
|
|||
|
|
@ -1,8 +1,18 @@
|
|||
#ifndef TYPES_H
|
||||
#define TYPES_H
|
||||
typedef unsigned char u8;
|
||||
typedef unsigned short u16;
|
||||
typedef unsigned long u32;
|
||||
typedef unsigned long size_t;
|
||||
#define NULL (0)
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
typedef uint8_t u8;
|
||||
typedef int8_t s8;
|
||||
typedef uint16_t u16;
|
||||
typedef int16_t s16;
|
||||
typedef uint32_t u32;
|
||||
typedef int32_t s32;
|
||||
typedef uint64_t u64;
|
||||
typedef int64_t s64;
|
||||
|
||||
/* FIXME is BITS_PER_LONG needed? */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue