diff --git a/src/arch/alpha/include/arch/boot/boot.h b/src/arch/alpha/include/arch/boot/boot.h
new file mode 100644
index 0000000000..1d2e998cd0
--- /dev/null
+++ b/src/arch/alpha/include/arch/boot/boot.h
@@ -0,0 +1,9 @@
+#ifndef ASM_ALPHA_BOOT_H
+#define ASM_ALPHA_BOOT_H
+
+#define UBE64
+#define ELF_CLASS	ELFCLASS64
+#define ELF_DATA	ELFDATA2LSB
+#define ELF_ARCH	EM_ALPHA
+
+#endif /* ASM_ALPHA_BOOT_H */
diff --git a/src/arch/alpha/include/arch/boot/hwrpb.h b/src/arch/alpha/include/arch/boot/hwrpb.h
new file mode 100644
index 0000000000..4a7c5a4001
--- /dev/null
+++ b/src/arch/alpha/include/arch/boot/hwrpb.h
@@ -0,0 +1,204 @@
+#ifndef BOOT_HWRPB_H
+#define BOOT_HWRPB_H
+
+#define INIT_HWRPB ((struct hwrpb_struct *) 0x10000000)
+
+/*
+ * DEC processor types for Alpha systems.  Found in HWRPB.
+ * These values are architected.
+ */
+
+#define EV3_CPU                 1       /* EV3                  */
+#define EV4_CPU                 2       /* EV4 (21064)          */
+#define LCA4_CPU                4       /* LCA4 (21066/21068)   */
+#define EV5_CPU                 5       /* EV5 (21164)          */
+#define EV45_CPU                6       /* EV4.5 (21064/xxx)    */
+#define EV56_CPU		7	/* EV5.6 (21164)	*/
+#define EV6_CPU			8	/* EV6 (21264)		*/
+#define PCA56_CPU		9	/* PCA56 (21164PC)	*/
+#define PCA57_CPU		10	/* PCA57 (notyet)	*/
+#define EV67_CPU		11	/* EV67 (21264A)	*/
+
+/*
+ * DEC system types for Alpha systems.  Found in HWRPB.
+ * These values are architected.
+ */
+
+#define ST_ADU			  1	/* Alpha ADU systype	*/
+#define ST_DEC_4000		  2	/* Cobra systype	*/
+#define ST_DEC_7000		  3	/* Ruby systype		*/
+#define ST_DEC_3000_500		  4	/* Flamingo systype	*/
+#define ST_DEC_2000_300		  6	/* Jensen systype	*/
+#define ST_DEC_3000_300		  7	/* Pelican systype	*/
+#define ST_DEC_2100_A500	  9	/* Sable systype	*/
+#define ST_DEC_AXPVME_64	 10	/* AXPvme system type	*/
+#define ST_DEC_AXPPCI_33	 11	/* NoName system type	*/
+#define ST_DEC_TLASER		 12	/* Turbolaser systype	*/
+#define ST_DEC_2100_A50		 13	/* Avanti systype	*/
+#define ST_DEC_MUSTANG		 14	/* Mustang systype	*/
+#define ST_DEC_ALCOR		 15	/* Alcor (EV5) systype	*/
+#define ST_DEC_1000		 17	/* Mikasa systype	*/
+#define ST_DEC_EB64		 18	/* EB64 systype		*/
+#define ST_DEC_EB66		 19	/* EB66 systype		*/
+#define ST_DEC_EB64P		 20	/* EB64+ systype	*/
+#define ST_DEC_BURNS		 21	/* laptop systype	*/
+#define ST_DEC_RAWHIDE		 22	/* Rawhide systype	*/
+#define ST_DEC_K2		 23	/* K2 systype		*/
+#define ST_DEC_LYNX		 24	/* Lynx systype		*/
+#define ST_DEC_XL		 25	/* Alpha XL systype	*/
+#define ST_DEC_EB164		 26	/* EB164 systype	*/
+#define ST_DEC_NORITAKE		 27	/* Noritake systype	*/
+#define ST_DEC_CORTEX		 28	/* Cortex systype	*/
+#define ST_DEC_MIATA		 30	/* Miata systype        */
+#define ST_DEC_XXM		 31	/* XXM systype		*/
+#define ST_DEC_TAKARA		 32	/* Takara systype	*/
+#define ST_DEC_YUKON		 33	/* Yukon systype	*/
+#define ST_DEC_TSUNAMI		 34	/* Tsunami systype	*/
+#define ST_DEC_WILDFIRE		 35	/* Wildfire systype	*/
+#define ST_DEC_CUSCO		 36	/* CUSCO systype	*/
+#define ST_DEC_EIGER		 37	/* Eiger systype	*/
+#define ST_DEC_TITAN		 38	/* Titan systype	*/
+
+/* UNOFFICIAL!!! */
+#define ST_UNOFFICIAL_BIAS	100
+#define ST_DTI_RUFFIAN		101	/* RUFFIAN systype	*/
+
+/* Alpha Processor, Inc. systems */
+#define ST_API_BIAS		200
+#define ST_API_NAUTILUS		201	/* UP1000 systype	*/
+
+struct pcb_struct {
+	unsigned long ksp;
+	unsigned long usp;
+	unsigned long ptbr;
+	unsigned int pcc;
+	unsigned int asn;
+	unsigned long unique;
+	unsigned long flags;
+	unsigned long res1, res2;
+};
+
+struct percpu_struct {
+	unsigned long hwpcb[16];
+	unsigned long flags;
+	unsigned long pal_mem_size;
+	unsigned long pal_scratch_size;
+	unsigned long pal_mem_pa;
+	unsigned long pal_scratch_pa;
+	unsigned long pal_revision;
+	unsigned long type;
+	unsigned long variation;
+	unsigned long revision;
+	unsigned long serial_no[2];
+	unsigned long logout_area_pa;
+	unsigned long logout_area_len;
+	unsigned long halt_PCBB;
+	unsigned long halt_PC;
+	unsigned long halt_PS;
+	unsigned long halt_arg;
+	unsigned long halt_ra;
+	unsigned long halt_pv;
+	unsigned long halt_reason;
+	unsigned long res;
+	unsigned long ipc_buffer[21];
+	unsigned long palcode_avail[16];
+	unsigned long compatibility;
+};
+
+struct procdesc_struct {
+	unsigned long weird_vms_stuff;
+	unsigned long address;
+};
+
+struct vf_map_struct {
+	unsigned long va;
+	unsigned long pa;
+	unsigned long count;
+};
+
+struct crb_struct {
+	struct procdesc_struct * dispatch_va;
+	struct procdesc_struct * dispatch_pa;
+	struct procdesc_struct * fixup_va;
+	struct procdesc_struct * fixup_pa;
+	/* virtual->physical map */
+	unsigned long map_entries;
+	unsigned long map_pages;
+	struct vf_map_struct map[1];
+};
+
+struct memclust_struct {
+	unsigned long start_pfn;
+	unsigned long numpages;
+	unsigned long numtested;
+	unsigned long bitmap_va;
+	unsigned long bitmap_pa;
+	unsigned long bitmap_chksum;
+	unsigned long usage;
+};
+
+struct memdesc_struct {
+	unsigned long chksum;
+	unsigned long optional_pa;
+	unsigned long numclusters;
+	struct memclust_struct cluster[0];
+};
+
+struct dsr_struct {
+	long smm;			/* SMM nubber used by LMF       */
+	unsigned long  lurt_off;	/* offset to LURT table         */
+	unsigned long  sysname_off;	/* offset to sysname char count */
+};
+
+struct hwrpb_struct {
+	unsigned long phys_addr;	/* check: physical address of the hwrpb */
+	unsigned long id;		/* check: "HWRPB\0\0\0" */
+	unsigned long revision;	
+	unsigned long size;		/* size of hwrpb */
+	unsigned long cpuid;
+	unsigned long pagesize;		/* 8192, I hope */
+	unsigned long pa_bits;		/* number of physical address bits */
+	unsigned long max_asn;
+	unsigned char ssn[16];		/* system serial number: big bother is watching */
+	unsigned long sys_type;
+	unsigned long sys_variation;
+	unsigned long sys_revision;
+	unsigned long intr_freq;	/* interval clock frequency * 4096 */
+	unsigned long cycle_freq;	/* cycle counter frequency */
+	unsigned long vptb;		/* Virtual Page Table Base address */
+	unsigned long res1;
+	unsigned long tbhb_offset;	/* Translation Buffer Hint Block */
+	unsigned long nr_processors;
+	unsigned long processor_size;
+	unsigned long processor_offset;
+	unsigned long ctb_nr;
+	unsigned long ctb_size;		/* console terminal block size */
+	unsigned long ctbt_offset;	/* console terminal block table offset */
+	unsigned long crb_offset;	/* console callback routine block */
+	unsigned long mddt_offset;	/* memory data descriptor table */
+	unsigned long cdb_offset;	/* configuration data block (or NULL) */
+	unsigned long frut_offset;	/* FRU table (or NULL) */
+	void (*save_terminal)(unsigned long);
+	unsigned long save_terminal_data;
+	void (*restore_terminal)(unsigned long);
+	unsigned long restore_terminal_data;
+	void (*CPU_restart)(unsigned long);
+	unsigned long CPU_restart_data;
+	unsigned long res2;
+	unsigned long res3;
+	unsigned long chksum;
+	unsigned long rxrdy;
+	unsigned long txrdy;
+	unsigned long dsr_offset;	/* "Dynamic System Recognition Data Block Table" */
+};
+
+static inline void
+hwrpb_update_checksum(struct hwrpb_struct *h)
+{
+	unsigned long sum = 0, *l;
+        for (l = (unsigned long *) h; l < (unsigned long *) &h->chksum; ++l)
+                sum += *l;
+        h->chksum = sum;
+}
+
+#endif /* BOOT_HWRPB_H */
diff --git a/src/arch/alpha/include/stddef.h b/src/arch/alpha/include/stddef.h
new file mode 100644
index 0000000000..37ee13858a
--- /dev/null
+++ b/src/arch/alpha/include/stddef.h
@@ -0,0 +1,15 @@
+#ifndef ALPHA_STDDEF_H
+#define ALPHA_STDDEF_H
+
+typedef long ptrdiff_t;
+typedef unsigned long size_t;
+typedef long ssize_t;
+
+typedef int wchar_t;
+typedef unsigned int wint_t;
+
+#define NULL 0
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#endif /* ALPHA_STDDEF_H */
diff --git a/src/arch/alpha/include/stdint.h b/src/arch/alpha/include/stdint.h
new file mode 100644
index 0000000000..9b93a0c84f
--- /dev/null
+++ b/src/arch/alpha/include/stdint.h
@@ -0,0 +1,53 @@
+#ifndef ALPHA_STDINT_H
+#define ALPHA_STDINT_H
+
+/* Exact integral types */
+typedef unsigned char      uint8_t;
+typedef signed char        int8_t; 
+
+typedef unsigned short     uint16_t;
+typedef signed short       int16_t;
+
+typedef unsigned int       uint32_t;
+typedef signed int         int32_t;
+
+typedef unsigned long      uint64_t;
+typedef signed long        int64_t;
+
+
+/* Small types */
+typedef unsigned char      uint_least8_t;
+typedef signed char        int_least8_t; 
+
+typedef unsigned short     uint_least16_t;
+typedef signed short       int_least16_t;
+
+typedef unsigned int       uint_least32_t;
+typedef signed int         int_least32_t;
+
+typedef unsigned long      uint_least64_t;
+typedef signed long        int_least64_t;
+
+/* Fast Types */
+typedef unsigned char      uint_fast8_t;
+typedef signed char        int_fast8_t; 
+
+typedef unsigned long      uint_fast16_t;
+typedef signed long        int_fast16_t;
+
+typedef unsigned long      uint_fast32_t;
+typedef signed long        int_fast32_t;
+
+typedef unsigned long      uint_fast64_t;
+typedef signed long        int_fast64_t;
+
+/* Types for `void *' pointers.  */
+typedef long               intptr_t;
+typedef unsigned long      uintptr_t;
+
+/* Largest integral types */
+typedef long               intmax_t;
+typedef unsigned long      uintmax_t;
+
+
+#endif /* ALPHA_STDINT_H */
diff --git a/src/arch/i386/Config b/src/arch/i386/Config
new file mode 100644
index 0000000000..9a6e1d85a9
--- /dev/null
+++ b/src/arch/i386/Config
@@ -0,0 +1,2 @@
+makedefine ARCH=i386
+dir boot
diff --git a/src/arch/i386/boot/Config b/src/arch/i386/boot/Config
new file mode 100644
index 0000000000..178df54605
--- /dev/null
+++ b/src/arch/i386/boot/Config
@@ -0,0 +1 @@
+object boot.o
diff --git a/src/arch/i386/boot/boot.c b/src/arch/i386/boot/boot.c
new file mode 100644
index 0000000000..b3c4b06aab
--- /dev/null
+++ b/src/arch/i386/boot/boot.c
@@ -0,0 +1,92 @@
+#include <boot/uniform_boot.h>
+#include <boot/elf.h>
+
+#ifndef CMD_LINE
+#define CMD_LINE ""
+#endif
+
+/* FIXME: the current placement of ube_all could lead to problems... 
+ * It should be in a location normally reserved for the bios.
+ */
+
+static struct {
+	struct uniform_boot_header header;
+	struct {
+		struct {
+			struct ube_memory memory;
+			struct ube_memory_range range[2];
+		} mem;
+	}env;
+	unsigned char command_line[1024];
+} ube_all = {
+	.header = {
+		.header_bytes = sizeof(ube_all.header),
+		.header_checksum = 0,
+		.arg = (unsigned long)&ube_all.command_line,
+		.arg_bytes = sizeof(ube_all.command_line),
+		.env = (unsigned long)&ube_all.env,
+		.env_bytes = sizeof(ube_all.env),
+	},
+	.env = {
+		.mem = {
+			.memory = {
+				.tag = UBE_TAG_MEMORY,
+				.size = sizeof(ube_all.env.mem),
+			},
+			.range = {
+#if 0
+				{
+					.start = 0,
+					.size = 0xa0000, /* 640k */
+					.type = UBE_MEM_RAM,
+				},
+#else
+				{
+					.start = 4096,	/* skip the first page */
+					.size = 0x9f000, /* 640k */
+					.type = UBE_MEM_RAM,
+				},
+#endif
+				{
+					.start = 0x00100000, /* 1M */
+					.size = 0, /* Fill in the size */
+					.type = UBE_MEM_RAM,
+				},
+			},
+		},
+		
+	},
+	.command_line = CMD_LINE,
+};
+
+void *get_ube_pointer(unsigned long totalram)
+{
+	ube_all.env.mem.range[1].size = ((totalram - 1024) << 10);
+	ube_all.header.header_checksum = 0;
+	ube_all.header.header_checksum = 
+		uniform_boot_compute_header_checksum(&ube_all.header);
+	return &ube_all.header;
+}
+
+int elf_check_arch(Elf_ehdr *ehdr)
+{
+	return (
+		((ehdr->e_machine == EM_386) ||	(ehdr->e_machine == EM_486)) &&
+		(ehdr->e_ident[EI_CLASS] == ELFCLASS32) &&
+		(ehdr->e_ident[EI_DATA] == ELFDATA2LSB) 
+		);
+	
+}
+
+void jmp_to_elf_entry(void *entry, void *ube)
+{
+	unsigned long type = 0x0A11B007;
+
+	/* Jump to kernel */
+	__asm__ __volatile__(
+		"pushl %0\n\t"
+		"ret\n\t"
+		:: "g" (entry), "a"(type), "b"(ube));
+}
+
+
diff --git a/src/arch/i386/include/arch/boot/boot.h b/src/arch/i386/include/arch/boot/boot.h
new file mode 100644
index 0000000000..0b9ef3b491
--- /dev/null
+++ b/src/arch/i386/include/arch/boot/boot.h
@@ -0,0 +1,9 @@
+#ifndef ASM_I386_BOOT_H
+#define ASM_I386_BOOT_H
+
+#define UBE32
+#define ELF_CLASS	ELFCLASS32
+#define ELF_DATA	ELFDATA2LSB
+#define ELF_ARCH	EM_386
+
+#endif /* ASM_I386_BOOT_H */
diff --git a/src/arch/i386/include/stddef.h b/src/arch/i386/include/stddef.h
new file mode 100644
index 0000000000..88a3b48957
--- /dev/null
+++ b/src/arch/i386/include/stddef.h
@@ -0,0 +1,15 @@
+#ifndef I386_STDDEF_H
+#define I386_STDDEF_H
+
+typedef long ptrdiff_t;
+typedef unsigned long size_t;
+typedef long ssize_t;
+
+typedef int wchar_t;
+typedef unsigned int wint_t;
+
+#define NULL 0
+
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#endif I386_STDDEF_H
diff --git a/src/arch/i386/include/stdint.h b/src/arch/i386/include/stdint.h
new file mode 100644
index 0000000000..58d7519cde
--- /dev/null
+++ b/src/arch/i386/include/stdint.h
@@ -0,0 +1,52 @@
+#ifndef I386_STDINT_H
+#define I386_STDINT_H
+
+/* Exact integral types */
+typedef unsigned char      uint8_t;
+typedef signed char        int8_t; 
+
+typedef unsigned short     uint16_t;
+typedef signed short       int16_t;
+
+typedef unsigned int       uint32_t;
+typedef signed int         int32_t;
+
+typedef unsigned long long uint64_t;
+typedef signed long long   int64_t;
+
+/* Small types */
+typedef unsigned char      uint_least8_t;
+typedef signed char        int_least8_t; 
+
+typedef unsigned short     uint_least16_t;
+typedef signed short       int_least16_t;
+
+typedef unsigned int       uint_least32_t;
+typedef signed int         int_least32_t;
+
+typedef unsigned long long uint_least64_t;
+typedef signed long long   int_least64_t;
+
+/* Fast Types */
+typedef unsigned char      uint_fast8_t;
+typedef signed char        int_fast8_t; 
+
+typedef unsigned int       uint_fast16_t;
+typedef signed int         int_fast16_t;
+
+typedef unsigned int       uint_fast32_t;
+typedef signed int         int_fast32_t;
+
+typedef unsigned long long uint_fast64_t;
+typedef signed long long   int_fast64_t;
+
+/* Types for `void *' pointers.  */
+typedef int                intptr_t;
+typedef unsigned int       uintptr_t;
+
+/* Largest integral types */
+typedef long long int      intmax_t;
+typedef unsigned long long uintmax_t;
+
+
+#endif /* I386_STDINT_H */
diff --git a/src/cpu/ev6/dc21264.h b/src/cpu/ev6/dc21264.h
new file mode 100644
index 0000000000..bb1016feb3
--- /dev/null
+++ b/src/cpu/ev6/dc21264.h
@@ -0,0 +1,637 @@
+#ifndef CPU_DC21264_H
+#define CPU_DC21264_H
+
+/*
+ * src/cpu/ev6/dc21264.h
+ *
+ * Copyright (C) 2001 Linux Networx
+ *
+ */
+
+
+/* 
+ * Ebox IPR scorboard bits 
+ * =========================================================
+ */
+#define EV6_SCB__CC		(1 << 5)
+#define EV6_SCB__CC_CTL		(1 << 5)
+#define EV6_SCB__VA		((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7))
+#define EV6_SCB__VA_CTL		(1 << 5)
+#define EV6_SCB__VA_FORM	((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7))
+
+/* 
+ * Ibox IPR scorboard bits 
+ * =========================================================
+ */
+#define EV6_SCB__ITB_TAG	(1 << 6)
+#define EV6_SCB__ITB_PTE	((1 << 0) | (1 << 4))
+#define EV6_SCB__ITB_IAP	(1 << 4)
+#define EV6_SCB__ITB_IA		(1 << 4)
+#define EV6_SCB__ITB_IS		((1 << 4) | (1 << 6))
+#define EV6_SCB__EXC_ADDR	0
+#define EV6_SCB__IVA_FORM	(1 << 5)
+#define EV6_SCB__CM		(1 << 4)
+#define EV6_SCB__IER		(1 << 4)
+#define EV6_SCB__IER_CM		(1 << 4)
+#define EV6_SCB__SIRR		(1 << 4)
+#define EV6_SCB__ISUM		0
+#define EV6_SCB__HW_INT_CLR	(1 << 4)
+#define EV6_SCB__EXC_SUM	0
+#define EV6_SCB__PAL_BASE	(1 << 4)
+#define EV6_SCB__I_CTL		(1 << 4)
+#define EV6_SCB__I_STAT		(1 << 4)
+#define EV6_SCB__IC_FLUSH	(1 << 4)
+#define EV6_SCB__IC_FLUSH_ASM	(1 << 4)
+#define EV6_SCB__CLR_MAP	((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7))
+#define EV6_SCB__SLEEP		((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7))
+#define EV6_SCB__PCTX		(1 << 4)
+#define EV6_SCB__PCTR_CTL	(1 << 4)
+
+/* 
+ * Mbox IPR scorboard bits 
+ * =========================================================
+ */
+#define EV6_SCB__DTB_TAG0	((1 << 2) | (1 << 6))
+#define EV6_SCB__DTB_TAG1	((1 << 1) | (1 << 5))
+#define EV6_SCB__DTB_PTE0	((1 << 0) | (1 << 4))
+#define EV6_SCB__DTB_PTE1	((1 << 3) | (1 << 7))
+#define EV6_SCB__DTB_ALTMODE	(1 << 6)
+#define EV6_SCB__DTB_IAP	(1 << 7)
+#define EV6_SCB__DTB_IA		(1 << 7)
+#define EV6_SCB__DTB_IS0	(1 << 6)
+#define EV6_SCB__DTB_IS1	(1 << 7)
+#define EV6_SCB__DTB_ASN0	(1 << 4)
+#define EV6_SCB__DTB_ASN1	(1 << 7)
+#define EV6_SCB__MM_STAT	0
+#define EV6_SCB__M_CTL		(1 << 6)
+#define EV6_SCB__DC_CTL		(1 << 6)
+#define EV6_SCB__DC_STAT	(1 << 6)
+
+/* 
+ * Cbox IPR scorboard bits 
+ * =========================================================
+ */
+
+#define EV6_SCB__C_DATA		(1 << 6)
+#define EV6_SCB__C_SHFT		(1 << 6)
+
+/* 
+ * Ebox IPRs 
+ * =========================================================
+ */
+#define EV6__CC			((0xC0 << 8) | EV6_SCB__CC)
+#define EV6__CTL		((0xC1 << 8) | EV6_SCB__CTL) 
+#define EV6__VA			((0xC2 << 8) | EV6_SCB__VA)
+#define EV6__VA_CTL		((0xC4 << 8) | EV6_SCB__VA_CTL)
+#define EV6__VA_FORM		((0xC3 << 8) | EV6_SCB__VA_FORM)
+
+/* 
+ * Ibox IPRs 
+ * =========================================================
+ */
+#define EV6__ITB_TAG		((0x00 << 8) | EV6_SCB__ITB_TAG)
+#define EV6__ITB_PTE		((0x01 << 8) | EV6_SCB__ITB_PTE)
+#define EV6__ITB_IAP		((0x02 << 8) | EV6_SCB__ITB_IAP)
+#define EV6__ITB_IA		((0x03 << 8) | EV6_SCB__ITB_IA)
+#define EV6__ITB_IS		((0x04 << 8) | EV6_SCB__ITB_IS)
+#define EV6__EXC_ADDR		((0x06 << 8) | EV6_SCB__EXC_ADDR)
+#define EV6__IVA_FORM		((0x07 << 8) | EV6_SCB__IVA_FORM)
+#define EV6__CM			((0x09 << 8) | EV6_SCB__CM)
+#define EV6__IER		((0x0A << 8) | EV6_SCB__IER)
+#define EV6__IER_CM		((0x0B << 8) | EV6_SCB__IER_CM)
+#define EV6__SIRR		((0x0C << 8) | EV6_SCB__SIRR)
+#define EV6__ISUM		((0x0D << 8) | EV6_SCB__ISUM)
+#define EV6__HW_INT_CLR		((0x0E << 8) | EV6_SCB__HW_INT_CLR)
+#define EV6__EXC_SUM		((0x0F << 8) | EV6_SCB__EXC_SUM)
+#define EV6__PAL_BASE		((0x10 << 8) | EV6_SCB__PAL_BASE)
+#define EV6__I_CTL		((0x11 << 8) | EV6_SCB__I_CTL)
+#define EV6__I_STAT		((0x16 << 8) | EV6_SCB__I_STAT)
+#define EV6__IC_FLUSH		((0x13 << 8) | EV6_SCB__IC_FLUSH)
+#define EV6__IC_FLUSH_ASM	((0x12 << 8) | EV6_SCB__IC_FLUSH_ASM)
+#define EV6__CLR_MAP		((0x15 << 8) | EV6_SCB__CLR_MAP)
+#define EV6__SLEEP		((0x17 << 8) | EV6_SCB__SLEEP)
+#define EV6__PCTX		((0x5f << 8) | EV6_SCB__PCTX)
+#define EV6__PCTR_CTL		((0x14 << 8) | EV6_SCB__PCTR_CTL)
+
+/* 
+ * Mbox IPRs 
+ * =========================================================
+ */
+#define EV6__DTB_TAG0		((0x20 << 8) | EV6_SCB__DTB_TAG0)
+#define EV6__DTB_TAG1		((0xA0 << 8) | EV6_SCB__DTB_TAG1)
+#define EV6__DTB_PTE0		((0x21 << 8) | EV6_SCB__DTB_PTE0)
+#define EV6__DTB_PTE1		((0xA1 << 8) | EV6_SCB__DTB_PTE1)
+#define EV6__DTB_ALTMODE	((0x26 << 8) | EV6_SCB__DTB_ALTMODE)
+#define EV6__DTB_IAP		((0xA2 << 8) | EV6_SCB__DTB_IAP)
+#define EV6__DTB_IA		((0xA3 << 8) | EV6_SCB__DTB_IA)
+#define EV6__DTB_IS0		((0x24 << 8) | EV6_SCB__DTB_IS0)
+#define EV6__DTB_IS1		((0xA4 << 8) | EV6_SCB__DTB_IS1)
+#define EV6__DTB_ASN0		((0x25 << 8) | EV6_SCB__DTB_ASN0)
+#define EV6__DTB_ASN1		((0xA5 << 8) | EV6_SCB__DTB_ASN1)
+#define EV6__MM_STAT		((0x27 << 8) | EV6_SCB__MM_STAT)
+#define EV6__M_CTL		((0x28 << 8) | EV6_SCB__M_CTL)
+#define EV6__DC_CTL		((0x29 << 8) | EV6_SCB__DC_CTL)
+#define EV6__DC_STAT		((0x2A << 8) | EV6_SCB__DC_STAT)
+
+/* 
+ * Cbox IPRs 
+ * =========================================================
+ */
+#define EV6__C_DATA		((0x2B << 8) | EV6_SCB__C_DATA)
+#define EV6__C_SHFT		((0x2C << 8) | EV6_SCB__C_SHFT)
+
+/* 
+ * Ebox IPR fields 
+ * =========================================================
+ */
+
+/* EV6__CC */
+#define EV6__CC__COUNTER__S	0
+#define EV6__CC__COUNTER__V	32
+#define EV6__CC__COUNTER__M	((1 << EV6__CC__COUNTER__V) -1)
+
+#define EV6__CC__OFFSET__S	32
+#define EV6__CC__OFFSET__V	32
+#define EV6__CC__OFFSET__M	((1 << EV6__CC__OFFSET__V) -1)
+
+/* EV6__CC_CTL */
+#define EV6__CC_CTL__COUNTER__S	4
+#define EV6__CC_CTL__COUNTER__V	1
+#define EV6__CC_CTL__COUNTER__M	((1 << EV6__CC_CTL__COUNTER__V) -1)
+
+#define EV6__CC_CTL__CC_ENA__S	32
+#define EV6__CC_CTL__CC_ENA__V	28
+#define EV6__CC_CTL__CC_ENA__M	((1 << EV6__CC_CTL__CC_ENA__V) -1)
+
+/* EV6__VA (no sub fields) */
+
+/* EV6__VA_CTL */
+#define EV6__VA_CTL__B_ENDIAN__S	0
+#define EV6__VA_CTL__B_ENDIAN__V	1
+#define EV6__VA_CTL__B_ENDIAN__M	((1 << EV6__VA_CTL__B_ENDIAN__V) -1)
+#define EV6__VA_CTL__VA_48__S		1
+#define EV6__VA_CTL__VA_48__V		1
+#define EV6__VA_CTL__VA_48__M		((1 << EV6__VA_CTL__VA_48__V) -1)
+#define EV6__VA_CTL__VA_FORM_32__S	2
+#define EV6__VA_CTL__VA_FORM_32__V	1
+#define EV6__VA_CTL__VA_FORM_32__M	((1 << EV6__VA_CTL__VA_FORM32__V) -1)
+#define EV6__VA_CTL__VPTB__S		30
+#define EV6__VA_CTL__VPTB__V		34
+#define EV6__VA_CTL__VPTB__M		((1 << EV6__VA_CTL__VPTB__V) -1)
+
+/* EV6__VA_FORM (no sub fields) */
+
+/* 
+ * Ibox IPR fields 
+ * =========================================================
+ */
+
+/* EV6__ITB_TAG (no subfields) */
+
+/* EV6__ITB_PTE */
+#define EV6__ITB_PTE__ASM__S	4
+#define EV6__ITB_PTE__ASM__V	1
+#define EV6__ITB_PTE__ASM__M	((1 << EV6__ITB_PTE__ASM__V) - 1)
+#define EV6__ITB_PTE__GH__S	5
+#define EV6__ITB_PTE__GH__V	2
+#define EV6__ITB_PTE__GH__M	((1 << EV6__ITB_PTE__GH__V) - 1)
+#define EV6__ITB_PTE__KRE__S	8
+#define EV6__ITB_PTE__KRE__V	1
+#define EV6__ITB_PTE__KRE__M	((1 << EV6__ITB_PTE__KRE__V) - 1)
+#define EV6__ITB_PTE__ERE__S	9
+#define EV6__ITB_PTE__ERE__V	1
+#define EV6__ITB_PTE__ERE__M	((1 << EV6__ITB_PTE__ERE__V) - 1)
+#define EV6__ITB_PTE__SRE__S	10
+#define EV6__ITB_PTE__SRE__V	1
+#define EV6__ITB_PTE__SRE__M	((1 << EV6__ITB_PTE__SRE__V) - 1)
+#define EV6__ITB_PTE__URE__S	11
+#define EV6__ITB_PTE__URE__V	1
+#define EV6__ITB_PTE__URE__M	((1 << EV6__ITB_PTE__URE__V) - 1)
+#define EV6__ITB_PTE__PFN__S	13
+#define EV6__ITB_PTE__PFN__V	31
+#define EV6__ITB_PTE__PFN__M	((1 << EV6__ITB_PTE__PFN__V) - 1)
+
+/* EV6__ITB_IAP (no subfields) */
+/* EV6__ITB_IA (no subfields) */
+/* EV6__ITB_IS (no subfields */
+
+/* EV6__EXC_ADDR */
+#define EV6__EXC_ADDR__PAL__S	0
+#define EV6__EXC_ADDR__PAL__V	1
+#define EV6__EXC_ADDR__PAL__M	((1 << EV6__EXC_ADDR__PAL__V) -1)
+#define EV6__EXC_ADDR__PC__S	2
+#define EV6__EXC_ADDR__PC__V	2
+#define EV6__EXC_ADDR__PC__M	((1 << EV6__EXC_ADDR__PC__V) -1)
+
+/* EV6__IVA_FORM (no subfields) */
+
+/* EV6__IER_CM */
+#define EV6__IER_CM__CM__S	3
+#define EV6__IER_CM__CM__V	2
+#define EV6__IER_CM__CM__M	((1 << EV6__IER_CM__CM__M) -1)
+#define EV6__IER_CM__ASTEN__S	13
+#define EV6__IER_CM__ASTEN__V	1
+#define EV6__IER_CM__ASTEN__M	((1 << EV6__IER_CM__ASTEN__M) -1)
+#define EV6__IER_CM__SIEN__S	14
+#define EV6__IER_CM__SIEN__V	15
+#define EV6__IER_CM__SIEN__M	((1 << EV6__IER_CM__SIEN__M) -1)
+#define EV6__IER_CM__PCEN__S	29
+#define EV6__IER_CM__PCEN__V	2
+#define EV6__IER_CM__PCEN__M	((1 << EV6__IER_CM__PCEN__M) -1)
+#define EV6__IER_CM__CREN__S	31
+#define EV6__IER_CM__CREN__V	1
+#define EV6__IER_CM__CREN__M	((1 << EV6__IER_CM__CREN__M) -1)
+#define EV6__IER_CM__SLEN__S	32
+#define EV6__IER_CM__SLEN__V	1
+#define EV6__IER_CM__SLEN__M	((1 << EV6__IER_CM__SLEN__M) -1)
+#define EV6__IER_CM__EIEN__S	33
+#define EV6__IER_CM__EIEN__V	6
+#define EV6__IER_CM__EIEN__M	((1 << EV6__IER_CM__EIEN__M) -1)
+
+/* EV6__SIRR */
+#define EV6__SIRR__SIR__S	14
+#define EV6__SIRR__SIR__V	15
+#define EV6__SIRR__SIR__M	((1 << EV6__SIRR__SIR__V) -1)
+
+
+/* EV6__ISUM */
+#define EV6__ISUM__ASTK__S	3
+#define EV6__ISUM__ASTK__V	1
+#define EV6__ISUM__ASTK__M	((1 << EV6__ISUM__ASTK__V) -1)
+#define EV6__ISUM__ASTE__S	4
+#define EV6__ISUM__ASTE__V	4
+#define EV6__ISUM__ASTE__M	((1 << EV6__ISUM__ASTE__V) -1)
+#define EV6__ISUM__ASTS__S	1
+#define EV6__ISUM__ASTS__V	9
+#define EV6__ISUM__ASTS__M	((1 << EV6__ISUM__ASTS__V) -1)
+#define EV6__ISUM__ASTU__S	10
+#define EV6__ISUM__ASTU__V	1
+#define EV6__ISUM__ASTU__M	((1 << EV6__ISUM__ASTU__V) -1)
+#define EV6__ISUM__SI__S	14
+#define EV6__ISUM__SI__V	15
+#define EV6__ISUM__SI__M	((1 << EV6__ISUM__SI__V) -1)
+#define EV6__ISUM__PC__S	29
+#define EV6__ISUM__PC__V	2
+#define EV6__ISUM__PC__M	((1 << EV6__ISUM__PC__V) -1)
+#define EV6__ISUM__CR__S	31
+#define EV6__ISUM__CR__V	1
+#define EV6__ISUM__CR__M	((1 << EV6__ISUM__CR__V) -1)
+#define EV6__ISUM__SL__S	32
+#define EV6__ISUM__SL__V	1
+#define EV6__ISUM__SL__M	((1 << EV6__ISUM__SL__V) -1)
+#define EV6__ISUM__EI__S	33
+#define EV6__ISUM__EI__V	6
+#define EV6__ISUM__EI__M	((1 << EV6__ISUM__EI__V) -1)
+
+/* EV6__HW_INT_CLR */
+#define EV6__HW_INT_CLR__FBTP__S	26
+#define EV6__HW_INT_CLR__FBTP__V	1
+#define EV6__HW_INT_CLR__FBTP__M	((1 << EV6__HW_INT_CLR__FBTP__V) -1)
+#define EV6__HW_INT_CLR__MCHK_D__S	28
+#define EV6__HW_INT_CLR__MCHK_D__V	1
+#define EV6__HW_INT_CLR__MCHK_D__M	((1 << EV6__HW_INT_CLR__MCHK_D__V) -1)
+#define EV6__HW_INT_CLR__PC__S		29
+#define EV6__HW_INT_CLR__PC__V		2
+#define EV6__HW_INT_CLR__PC__M		((1 << EV6__HW_INT_CLR__PC__V) -1)
+#define EV6__HW_INT_CLR__CR__S		31
+#define EV6__HW_INT_CLR__CR__V		1
+#define EV6__HW_INT_CLR__CR__M		((1 << EV6__HW_INT_CLR__CR__V) -1)
+#define EV6__HW_INT_CLR__SL__S		32
+#define EV6__HW_INT_CLR__SL__V		1
+#define EV6__HW_INT_CLR__SL__M		((1 << EV6__HW_INT_CLR__SL__V) -1)
+
+/* EV6__EXC_SUM */
+#define EV6__EXC_SUM__SWC__S		0
+#define EV6__EXC_SUM__SWC__V		1
+#define EV6__EXC_SUM__SWC__M		((1 << EV6__EXC_SUM__SWC__V) -1)
+#define EV6__EXC_SUM__INV__S		1
+#define EV6__EXC_SUM__INV__V		1
+#define EV6__EXC_SUM__INV__M		((1 << EV6__EXC_SUM__INV__V) -1)
+#define EV6__EXC_SUM__DZE__S		2
+#define EV6__EXC_SUM__DZE__V		1
+#define EV6__EXC_SUM__DZE__M		((1 << EV6__EXC_SUM__DZE__V) -1)
+#define EV6__EXC_SUM__FOV__S		3
+#define EV6__EXC_SUM__FOV__V		1
+#define EV6__EXC_SUM__FOV__M		((1 << EV6__EXC_SUM__FOV__V) -1)
+#define EV6__EXC_SUM__UNF__S		4
+#define EV6__EXC_SUM__UNF__V		1
+#define EV6__EXC_SUM__UNF__M		((1 << EV6__EXC_SUM__UNF__V) -1)
+#define EV6__EXC_SUM__INE__S		5
+#define EV6__EXC_SUM__INE__V		1
+#define EV6__EXC_SUM__INE__M		((1 << EV6__EXC_SUM__INE__V) -1)
+#define EV6__EXC_SUM__IOV__S		6
+#define EV6__EXC_SUM__IOV__V		1
+#define EV6__EXC_SUM__IOV__M		((1 << EV6__EXC_SUM__IOV__V) -1)
+#define EV6__EXC_SUM__INT__S		7
+#define EV6__EXC_SUM__INT__V		1
+#define EV6__EXC_SUM__INT__M		((1 << EV6__EXC_SUM__INT__V) -1)
+#define EV6__EXC_SUM__REG__S		8
+#define EV6__EXC_SUM__REG__V		5
+#define EV6__EXC_SUM__REG__M		((1 << EV6__EXC_SUM__REG__V) -1)
+#define EV6__EXC_SUM__BAD_IVA__S	13
+#define EV6__EXC_SUM__BAD_IVA__V	1
+#define EV6__EXC_SUM__BAD_IVA__M	((1 << EV6__EXC_SUM__BAD_IVA__V) -1)
+#define EV6__EXC_SUM__PC_OVFL__S	41
+#define EV6__EXC_SUM__PC_OVFL__V	1
+#define EV6__EXC_SUM__PC_OVFL__M	((1 << EV6__EXC_SUM__PC_OVFL__V) -1)
+#define EV6__EXC_SUM__SET_INV__S	42
+#define EV6__EXC_SUM__SET_INV__V	1
+#define EV6__EXC_SUM__SET_INV__M	((1 << EV6__EXC_SUM__SET_INV__V) -1)
+#define EV6__EXC_SUM__SET_DZE__S	43
+#define EV6__EXC_SUM__SET_DZE__V	1
+#define EV6__EXC_SUM__SET_DZE__M	((1 << EV6__EXC_SUM__SET_DZE__V) -1)
+#define EV6__EXC_SUM__SET_OVF__S	44
+#define EV6__EXC_SUM__SET_OVF__V	1
+#define EV6__EXC_SUM__SET_OVF__M	((1 << EV6__EXC_SUM__SET_OVF__V) -1)
+#define EV6__EXC_SUM__SET_UNF__S	45
+#define EV6__EXC_SUM__SET_UNF__V	1
+#define EV6__EXC_SUM__SET_UNF__M	((1 << EV6__EXC_SUM__SET_UNF__V) -1)
+#define EV6__EXC_SUM__SET_INE__S	46
+#define EV6__EXC_SUM__SET_INE__V	1
+#define EV6__EXC_SUM__SET_INE__M	((1 << EV6__EXC_SUM__SET_INE__V) -1)
+#define EV6__EXC_SUM__SET_IOV__S	47
+#define EV6__EXC_SUM__SET_IOV__V	1
+#define EV6__EXC_SUM__SET_IOV__M	((1 << EV6__EXC_SUM__SET_IOV__V) -1)
+#define EV6__EXC_SUM__SEXT__S		48
+#define EV6__EXC_SUM__SEXT__V		16
+#define EV6__EXC_SUM__SEXT__M		((1 << EV6__EXC_SUM__SEXT__V) -1)
+
+/* EV6__PAL_BASE (no subfields) */
+
+/* EV6__I_CTL */
+#define EV6__I_CTL__SPCE__S		0
+#define EV6__I_CTL__SPCE__V		1
+#define EV6__I_CTL__SPCE__M		((1 << EV6__I_CTL__SPCE__V) -1)
+#define EV6__I_CTL__IC_EN__S		1
+#define EV6__I_CTL__IC_EN__V		2
+#define EV6__I_CTL__IC_EN__M		((1 << EV6__I_CTL__IC_EN__V) -1)
+#define EV6__I_CTL__SPE__S		3
+#define EV6__I_CTL__SPE__V		3
+#define EV6__I_CTL__SPE__M		((1 << EV6__I_CTL__SPE__V) -1)
+#define EV6__I_CTL__SDE__S		6
+#define EV6__I_CTL__SDE__V		2
+#define EV6__I_CTL__SDE__M		((1 << EV6__I_CTL__SDE__V) -1)
+#define EV6__I_CTL__SBE__S		8
+#define EV6__I_CTL__SBE__V		2
+#define EV6__I_CTL__SBE__M		((1 << EV6__I_CTL__SBE__V) -1)
+#define EV6__I_CTL__BP_MODE__S		10
+#define EV6__I_CTL__BP_MODE__V		2
+#define EV6__I_CTL__BP_MODE__M		((1 << EV6__I_CTL__BP_MODE__V) -1)
+#define EV6__I_CTL__HWE__S		12
+#define EV6__I_CTL__HWE__V		1
+#define EV6__I_CTL__HWE__M		((1 << EV6__I_CTL__HWE__V) -1)
+#define EV6__I_CTL__SL_XMIT__S		13
+#define EV6__I_CTL__SL_XMIT__V		1
+#define EV6__I_CTL__SL_XMIT__M		((1 << EV6__I_CTL__SL_XMIT__V) -1)
+#define EV6__I_CTL__SL_RCV__S		14
+#define EV6__I_CTL__SL_RCV__V		1
+#define EV6__I_CTL__SL_RCV__M		((1 << EV6__I_CTL__SL_RCV__V) -1)
+#define EV6__I_CTL__VA_48__S		15
+#define EV6__I_CTL__VA_48__V		1
+#define EV6__I_CTL__VA_48__M		((1 << EV6__I_CTL__VA_48__V) -1)
+#define EV6__I_CTL__VA_FORM_32__S	16
+#define EV6__I_CTL__VA_FORM_32__V	1
+#define EV6__I_CTL__VA_FORM_32__M	((1 << EV6__I_CTL__VA_FORM_32__V) -1)
+#define EV6__I_CTL__SINGLE_ISSUE_H__S	17
+#define EV6__I_CTL__SINGLE_ISSUE_H__V	1
+#define EV6__I_CTL__SINGLE_ISSUE_H__M	((1 << EV6__I_CTL__SINGLE_ISSUE_H__V) -1)
+#define EV6__I_CTL__PCT0_EN__S		18
+#define EV6__I_CTL__PCT0_EN__V		1
+#define EV6__I_CTL__PCT0_EN__M		((1 << EV6__I_CTL__PCT0_EN__V) -1)
+#define EV6__I_CTL__PCT1_EN__S		19
+#define EV6__I_CTL__PCT1_EN__V		1
+#define EV6__I_CTL__PCT1_EN__M		((1 << EV6__I_CTL__PCT1_EN__V) -1)
+#define EV6__I_CTL__CALL_PAL_R23__S	20
+#define EV6__I_CTL__CALL_PAL_R23__V	1
+#define EV6__I_CTL__CALL_PAL_R23__M	((1 << EV6__I_CTL__CALL_PAL_R23__V) -1)
+#define EV6__I_CTL__MCHK_EN__S		21
+#define EV6__I_CTL__MCHK_EN__V		1
+#define EV6__I_CTL__MCHK_EN__M		((1 << EV6__I_CTL__MCHK_EN__V) -1)
+#define EV6__I_CTL__TB_MB_EN__S		22
+#define EV6__I_CTL__TB_MB_EN__V		1
+#define EV6__I_CTL__TB_MB_EN__M		((1 << EV6__I_CTL__TB_MB_EN__V) -1)
+#define EV6__I_CTL__BIST_FAIL__S	23
+#define EV6__I_CTL__BIST_FAIL__V	1
+#define EV6__I_CTL__BIST_FAIL__M	((1 << EV6__I_CTL__BIST_FAIL__V) -1)
+#define EV6__I_CTL__CHIP_ID__S		24
+#define EV6__I_CTL__CHIP_ID__V		6
+#define EV6__I_CTL__CHIP_ID__M		((1 << EV6__I_CTL__CHIP_ID__V) -1)
+#define EV6__I_CTL__VPTB__S		30
+#define EV6__I_CTL__VPTB__V		18
+#define EV6__I_CTL__VPTB__M		((1 << EV6__I_CTL__VPTB__V) -1)
+
+/* EV6__IC_FLUSH (no subfields)  */
+/* EV6__IC_FLUSH_ASM (no subfields) */
+/* EV6__CLR_MAP (no subfields */
+/* EV6__SLEEP (no subfields */
+
+/* EV6__PCTX */
+#define EV6__PCTX__PPCE__S	1
+#define EV6__PCTX__PPCE__V	1
+#define EV6__PCTX__PPCE__M	((1 << EV6__PCTX__PPCE__V) -1)
+#define EV6__PCTX__FPE__S	2
+#define EV6__PCTX__FPE__V	1
+#define EV6__PCTX__FPE__M	((1 << EV6__PCTX__FPE__V) -1)
+#define EV6__PCTX__ASTER__S	5
+#define EV6__PCTX__ASTER__V	4
+#define EV6__PCTX__ASTER__M	((1 << EV6__PCTX__ASTER__V) -1)
+#define EV6__PCTX__ASTRR__S	9
+#define EV6__PCTX__ASTRR__V	4
+#define EV6__PCTX__ASTRR__M	((1 << EV6__PCTX__ASTRR__V) -1)
+#define EV6__PCTX__ASN__S	39
+#define EV6__PCTX__ASN__V	8
+#define EV6__PCTX__ASN__M	((1 << EV6__PCTX__ASN__V) -1)
+
+
+/* EV6__PCTR_CTL */
+#define EV6__PCTR_CTL__SL1__S	0
+#define EV6__PCTR_CTL__SL1__V	4
+#define EV6__PCTR_CTL__SL1__M	((1 << EV6__PCTR_CTL__SL1__V) -1)
+#define EV6__PCTR_CTL__SL0__S	4
+#define EV6__PCTR_CTL__SL0__V	1
+#define EV6__PCTR_CTL__SL0__M	((1 << EV6__PCTR_CTL__SL0__V) -1)
+#define EV6__PCTR_CTL__PCTR1__S	6
+#define EV6__PCTR_CTL__PCTR1__V	20
+#define EV6__PCTR_CTL__PCTR1__M	((1 << EV6__PCTR_CTL__PCTR1__V) -1)
+#define EV6__PCTR_CTL__PCTR0__S	28
+#define EV6__PCTR_CTL__PCTR0__V	20
+#define EV6__PCTR_CTL__PCTR0__M	((1 << EV6__PCTR_CTL__PCTR0__V) -1)
+
+/* 
+ * Mbox IPR fields 
+ * =========================================================
+ */
+
+/* EV6__DTB_TAG0 (no subfields) */
+/* EV6__DTB_TAG1 (no subfields) */
+
+/* EV6__DTB_PTE0 */
+#define EV6__DTB_PTE0__FOR__S	1
+#define EV6__DTB_PTE0__FOR__V	1
+#define EV6__DTB_PTE0__FOR__M	((1 << EV6__DTB_PTE0__FOR__V) -1)
+#define EV6__DTB_PTE0__FOW__S	2
+#define EV6__DTB_PTE0__FOW__V	1
+#define EV6__DTB_PTE0__FOW__M	((1 << EV6__DTB_PTE0__FOW__V) -1)
+#define EV6__DTB_PTE0__ASM__S	4
+#define EV6__DTB_PTE0__ASM__V	1
+#define EV6__DTB_PTE0__ASM__M	((1 << EV6__DTB_PTE0__ASM__V) -1)
+#define EV6__DTB_PTE0__GH__S	5
+#define EV6__DTB_PTE0__GH__V	2
+#define EV6__DTB_PTE0__GH__M	((1 << EV6__DTB_PTE0__GH__V) -1)
+#define EV6__DTB_PTE0__KRE__S	8
+#define EV6__DTB_PTE0__KRE__V	1
+#define EV6__DTB_PTE0__KRE__M	((1 << EV6__DTB_PTE0__KRE__V) -1)
+#define EV6__DTB_PTE0__ERE__S	9
+#define EV6__DTB_PTE0__ERE__V	1
+#define EV6__DTB_PTE0__ERE__M	((1 << EV6__DTB_PTE0__ERE__V) -1)
+#define EV6__DTB_PTE0__SRE__S	10
+#define EV6__DTB_PTE0__SRE__V	1
+#define EV6__DTB_PTE0__SRE__M	((1 << EV6__DTB_PTE0__SRE__V) -1)
+#define EV6__DTB_PTE0__URE__S	11
+#define EV6__DTB_PTE0__URE__V	1
+#define EV6__DTB_PTE0__URE__M	((1 << EV6__DTB_PTE0__URE__V) -1)
+#define EV6__DTB_PTE0__KWE__S	12
+#define EV6__DTB_PTE0__KWE__V	1
+#define EV6__DTB_PTE0__KWE__M	((1 << EV6__DTB_PTE0__KEW__V) -1)
+#define EV6__DTB_PTE0__EWE__S	13
+#define EV6__DTB_PTE0__EWE__V	1
+#define EV6__DTB_PTE0__EWE__M	((1 << EV6__DTB_PTE0__EWE__V) -1)
+#define EV6__DTB_PTE0__SWE__S	14
+#define EV6__DTB_PTE0__SWE__V	1
+#define EV6__DTB_PTE0__SWE__M	((1 << EV6__DTB_PTE0__SWE__V) -1)
+#define EV6__DTB_PTE0__UWE__S	15
+#define EV6__DTB_PTE0__UWE__V	1
+#define EV6__DTB_PTE0__UWE__M	((1 << EV6__DTB_PTE0__UWE__V) -1)
+#define EV6__DTB_PTE0__PFN__S	32
+#define EV6__DTB_PTE0__PFN__V	31
+#define EV6__DTB_PTE0__PFN__M	((1 << EV6__DTB_PTE0__PA__V) -1)
+
+
+/* EV6__DTB_PTE1 */
+#define EV6__DTB_PTE1__FOR__S	1
+#define EV6__DTB_PTE1__FOR__V	1
+#define EV6__DTB_PTE1__FOR__M	((1 << EV6__DTB_PTE1__FOR__V) -1)
+#define EV6__DTB_PTE1__FOW__S	2
+#define EV6__DTB_PTE1__FOW__V	1
+#define EV6__DTB_PTE1__FOW__M	((1 << EV6__DTB_PTE1__FOW__V) -1)
+#define EV6__DTB_PTE1__ASM__S	4
+#define EV6__DTB_PTE1__ASM__V	1
+#define EV6__DTB_PTE1__ASM__M	((1 << EV6__DTB_PTE1__ASM__V) -1)
+#define EV6__DTB_PTE1__GH__S	5
+#define EV6__DTB_PTE1__GH__V	2
+#define EV6__DTB_PTE1__GH__M	((1 << EV6__DTB_PTE1__GH__V) -1)
+#define EV6__DTB_PTE1__KRE__S	8
+#define EV6__DTB_PTE1__KRE__V	1
+#define EV6__DTB_PTE1__KRE__M	((1 << EV6__DTB_PTE1__KRE__V) -1)
+#define EV6__DTB_PTE1__ERE__S	9
+#define EV6__DTB_PTE1__ERE__V	1
+#define EV6__DTB_PTE1__ERE__M	((1 << EV6__DTB_PTE1__ERE__V) -1)
+#define EV6__DTB_PTE1__SRE__S	10
+#define EV6__DTB_PTE1__SRE__V	1
+#define EV6__DTB_PTE1__SRE__M	((1 << EV6__DTB_PTE1__SRE__V) -1)
+#define EV6__DTB_PTE1__URE__S	11
+#define EV6__DTB_PTE1__URE__V	1
+#define EV6__DTB_PTE1__URE__M	((1 << EV6__DTB_PTE1__URE__V) -1)
+#define EV6__DTB_PTE1__KWE__S	12
+#define EV6__DTB_PTE1__KWE__V	1
+#define EV6__DTB_PTE1__KWE__M	((1 << EV6__DTB_PTE1__KEW__V) -1)
+#define EV6__DTB_PTE1__EWE__S	13
+#define EV6__DTB_PTE1__EWE__V	1
+#define EV6__DTB_PTE1__EWE__M	((1 << EV6__DTB_PTE1__EWE__V) -1)
+#define EV6__DTB_PTE1__SWE__S	14
+#define EV6__DTB_PTE1__SWE__V	1
+#define EV6__DTB_PTE1__SWE__M	((1 << EV6__DTB_PTE1__SWE__V) -1)
+#define EV6__DTB_PTE1__UWE__S	15
+#define EV6__DTB_PTE1__UWE__V	1
+#define EV6__DTB_PTE1__UWE__M	((1 << EV6__DTB_PTE1__UWE__V) -1)
+#define EV6__DTB_PTE1__PFN__S	32
+#define EV6__DTB_PTE1__PFN__V	31
+#define EV6__DTB_PTE1__PFN__M	((1 << EV6__DTB_PTE1__PA__V) -1)
+
+/* EV6__ALT_MODE (no subfields) */
+/* EV6__DTB_IAP (no subfields) */
+/* EV6__DTB_IA (no subfields) */
+/* EV6__DTB_IS0 (no subfields) */
+/* EV6__DTB_IS1 (no subfields) */
+
+/* EV6__DTB_ASN0 */
+#define EV6__DTB_ASN0__ASN__S	56
+#define EV6__DTB_ASN0__ASN__V	8
+#define EV6__DTB_ASN0__ASN__M	((1 << EV6__DTB_ASN0__ASN__V) -1)
+
+/* EV6__DTB_ASN1 */
+#define EV6__DTB_ASN1__ASN__S	56
+#define EV6__DTB_ASN1__ASN__V	8
+#define EV6__DTB_ASN1__ASN__M	((1 << EV6__DTB_ASN1__ASN__V) -1)
+
+/* EV6__MM_STAT */
+#define EV6__MM_STAT__WR__S		0
+#define EV6__MM_STAT__WR__V		1
+#define EV6__MM_STAT__WR__M		((1 << EV6__MM_STAT__WR__V) -1)
+#define EV6__MM_STAT__ACV__S		1
+#define EV6__MM_STAT__ACV__V		1
+#define EV6__MM_STAT__ACV__M		((1 << EV6__MM_STAT__ACV__V) -1)
+#define EV6__MM_STAT__FOR__S		2
+#define EV6__MM_STAT__FOR__V		1
+#define EV6__MM_STAT__FOR__M		((1 << EV6__MM_STAT__FOR__V) -1)
+#define EV6__MM_STAT__FOW__S		3
+#define EV6__MM_STAT__FOW__V		1
+#define EV6__MM_STAT__FOW__M		((1 << EV6__MM_STAT__FOW__V) -1)
+#define EV6__MM_STAT__OPCODE__S		4
+#define EV6__MM_STAT__OPCODE__V		6
+#define EV6__MM_STAT__OPCODE__M		((1 << EV6__MM_STAT__OPCODE__V) -1)
+#define EV6__MM_STAT__DC_TAG_PERR__S	10
+#define EV6__MM_STAT__DC_TAG_PERR__V	1
+#define EV6__MM_STAT__DC_TAG_PERR__M	((1 << EV6__MM_STAT__DC_TAG_PERR__V) -1)
+
+/* EV6__M_CTL */
+#define EV6__M_CTL__SPE__S	1
+#define EV6__M_CTL__SPE__V	3
+#define EV6__M_CTL__SPE__M	((1 << EV6__M_CTL__SPE__V)-1)
+
+/* EV6__DC_CTL */
+#define EV6__DC_CTL__SET_EN__S		0
+#define EV6__DC_CTL__SET_EN__V		2
+#define EV6__DC_CTL__SET_EN__M		(( 1 << EV6__DC_CTL__SET_EN__V) -1)
+#define EV6__DC_CTL__F_HIT__S		2
+#define EV6__DC_CTL__F_HIT__V		1
+#define EV6__DC_CTL__F_HIT__M		(( 1 << EV6__DC_CTL__F_HIT__V) -1)
+#define EV6__DC_CTL__F_BAD_TPAR__S	4
+#define EV6__DC_CTL__F_BAD_TPAR__V	1
+#define EV6__DC_CTL__F_BAD_TPAR__M	(( 1 << EV6__DC_CTL__F_BAD_TPAR__V) -1)
+#define EV6__DC_CTL__F_BAD_DECC__S	5
+#define EV6__DC_CTL__F_BAD_DECC__V	1
+#define EV6__DC_CTL__F_BAD_DECC__M	(( 1 << EV6__DC_CTL__F_BAD_DECC__V) -1)
+#define EV6__DC_CTL__DCTAG_PAR_EN__S	6
+#define EV6__DC_CTL__DCTAG_PAR_EN__V	1
+#define EV6__DC_CTL__DCTAG_PAR_EN__M	(( 1 << EV6__DC_CTL__DCTAG_PAR_EN__V) -1)
+#define EV6__DC_CTL__DCDAT_ERR_EN__S	7
+#define EV6__DC_CTL__DCDAT_ERR_EN__V	1
+#define EV6__DC_CTL__DCDAT_ERR_EN__M	(( 1 << EV6__DC_CTL__DCDAT_ERR_EN__V) -1)
+
+/* EV6__DC_STAT */
+#define EV6__DC_STAT__TPERR_P0__S	0
+#define EV6__DC_STAT__TPERR_P0__V	1
+#define EV6__DC_STAT__TPERR_P0__M	((1 << EV6__DC_STAT__TPERR_P0__V) -1)
+#define EV6__DC_STAT__TPERR_P1__S	1
+#define EV6__DC_STAT__TPERR_P1__V	1
+#define EV6__DC_STAT__TPERR_P1__M	((1 << EV6__DC_STAT__TPERR_P1__V) -1)
+#define EV6__DC_STAT__ECC_ERR_ST__S	2
+#define EV6__DC_STAT__ECC_ERR_ST__V	1
+#define EV6__DC_STAT__ECC_ERR_ST__M	((1 << EV6__DC_STAT__ECC_ERR_ST__V) -1)
+#define EV6__DC_STAT__ECC_ERR_LD__S	3
+#define EV6__DC_STAT__ECC_ERR_LD__V	1
+#define EV6__DC_STAT__ECC_ERR_LD__M	((1 << EV6__DC_STAT__ECC_ERR_LD__V) -1)
+#define EV6__DC_STAT__SEO__S		4
+#define EV6__DC_STAT__SEO__V		1
+#define EV6__DC_STAT__SEO__M		((1 << EV6__DC_STAT__SEO__V) -1)
+
+
+/* 
+ * Cbox IPR fields 
+ * =========================================================
+ */
+/* EV6__C_DATA (no subfields) */
+/* EV6__C_SHIFT (no subfields) */
+
+#endif /* DC21264_H */
diff --git a/src/cpu/p5/Config b/src/cpu/p5/Config
index bda55c403b..6f6564e595 100644
--- a/src/cpu/p5/Config
+++ b/src/cpu/p5/Config
@@ -1,3 +1,4 @@
 option i586
 object cpuid.o
 #object tsc.o
+dir /arch/i386
diff --git a/src/cpu/p6/Config b/src/cpu/p6/Config
index 78d3a6863d..4b09cd3b73 100644
--- a/src/cpu/p6/Config
+++ b/src/cpu/p6/Config
@@ -4,3 +4,4 @@ object microcode.o
 object mpspec.o
 object mtrr.o
 object l2_cache.o
+object ioapic.o
diff --git a/src/include/boot/elf.h b/src/include/boot/elf.h
new file mode 100644
index 0000000000..abc17b2bd5
--- /dev/null
+++ b/src/include/boot/elf.h
@@ -0,0 +1,393 @@
+#ifndef ELF_H
+#define	ELF_H
+
+/* Standard ELF types.  */
+
+#include <stdint.h>
+#include <arch/boot/boot.h>
+
+/* Type for a 16-bit quantity.  */
+typedef uint16_t Elf32_Half;
+typedef uint16_t Elf64_Half;
+
+/* Types for signed and unsigned 32-bit quantities.  */
+typedef uint32_t Elf32_Word;
+typedef	int32_t  Elf32_Sword;
+typedef uint32_t Elf64_Word;
+typedef	int32_t  Elf64_Sword;
+
+/* Types for signed and unsigned 64-bit quantities.  */
+typedef uint64_t Elf32_Xword;
+typedef	int64_t  Elf32_Sxword;
+typedef uint64_t Elf64_Xword;
+typedef	int64_t  Elf64_Sxword;
+
+/* Type of addresses.  */
+typedef uint32_t Elf32_Addr;
+typedef uint64_t Elf64_Addr;
+
+/* Type of file offsets.  */
+typedef uint32_t Elf32_Off;
+typedef uint64_t Elf64_Off;
+
+/* Type for section indices, which are 16-bit quantities.  */
+typedef uint16_t Elf32_Section;
+typedef uint16_t Elf64_Section;
+
+/* Type of symbol indices.  */
+typedef uint32_t Elf32_Symndx;
+typedef uint64_t Elf64_Symndx;
+
+
+/* The ELF file header.  This appears at the start of every ELF file.  */
+
+#define EI_NIDENT (16)
+
+typedef struct
+{
+  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
+  Elf32_Half	e_type;			/* Object file type */
+  Elf32_Half	e_machine;		/* Architecture */
+  Elf32_Word	e_version;		/* Object file version */
+  Elf32_Addr	e_entry;		/* Entry point virtual address */
+  Elf32_Off	e_phoff;		/* Program header table file offset */
+  Elf32_Off	e_shoff;		/* Section header table file offset */
+  Elf32_Word	e_flags;		/* Processor-specific flags */
+  Elf32_Half	e_ehsize;		/* ELF header size in bytes */
+  Elf32_Half	e_phentsize;		/* Program header table entry size */
+  Elf32_Half	e_phnum;		/* Program header table entry count */
+  Elf32_Half	e_shentsize;		/* Section header table entry size */
+  Elf32_Half	e_shnum;		/* Section header table entry count */
+  Elf32_Half	e_shstrndx;		/* Section header string table index */
+} Elf32_Ehdr;
+
+typedef struct
+{
+  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
+  Elf64_Half	e_type;			/* Object file type */
+  Elf64_Half	e_machine;		/* Architecture */
+  Elf64_Word	e_version;		/* Object file version */
+  Elf64_Addr	e_entry;		/* Entry point virtual address */
+  Elf64_Off	e_phoff;		/* Program header table file offset */
+  Elf64_Off	e_shoff;		/* Section header table file offset */
+  Elf64_Word	e_flags;		/* Processor-specific flags */
+  Elf64_Half	e_ehsize;		/* ELF header size in bytes */
+  Elf64_Half	e_phentsize;		/* Program header table entry size */
+  Elf64_Half	e_phnum;		/* Program header table entry count */
+  Elf64_Half	e_shentsize;		/* Section header table entry size */
+  Elf64_Half	e_shnum;		/* Section header table entry count */
+  Elf64_Half	e_shstrndx;		/* Section header string table index */
+} Elf64_Ehdr;
+
+/* Fields in the e_ident array.  The EI_* macros are indices into the
+   array.  The macros under each EI_* macro are the values the byte
+   may have.  */
+
+#define EI_MAG0		0		/* File identification byte 0 index */
+#define ELFMAG0		0x7f		/* Magic number byte 0 */
+
+#define EI_MAG1		1		/* File identification byte 1 index */
+#define ELFMAG1		'E'		/* Magic number byte 1 */
+
+#define EI_MAG2		2		/* File identification byte 2 index */
+#define ELFMAG2		'L'		/* Magic number byte 2 */
+
+#define EI_MAG3		3		/* File identification byte 3 index */
+#define ELFMAG3		'F'		/* Magic number byte 3 */
+
+/* Conglomeration of the identification bytes, for easy testing as a word.  */
+#define	ELFMAG		"\177ELF"
+#define	SELFMAG		4
+
+#define EI_CLASS	4		/* File class byte index */
+#define ELFCLASSNONE	0		/* Invalid class */
+#define ELFCLASS32	1		/* 32-bit objects */
+#define ELFCLASS64	2		/* 64-bit objects */
+#define ELFCLASSNUM	3
+
+#define EI_DATA		5		/* Data encoding byte index */
+#define ELFDATANONE	0		/* Invalid data encoding */
+#define ELFDATA2LSB	1		/* 2's complement, little endian */
+#define ELFDATA2MSB	2		/* 2's complement, big endian */
+#define ELFDATANUM	3
+
+#define EI_VERSION	6		/* File version byte index */
+					/* Value must be EV_CURRENT */
+
+#define EI_OSABI	7		/* OS ABI identification */
+#define ELFOSABI_SYSV		0	/* UNIX System V ABI */
+#define ELFOSABI_HPUX		1	/* HP-UX */
+#define ELFOSABI_ARM		97	/* ARM */
+#define ELFOSABI_STANDALONE	255	/* Standalone (embedded) application */
+
+#define EI_ABIVERSION	8		/* ABI version */
+
+#define EI_PAD		9		/* Byte index of padding bytes */
+
+/* Legal values for e_type (object file type).  */
+
+#define ET_NONE		0		/* No file type */
+#define ET_REL		1		/* Relocatable file */
+#define ET_EXEC		2		/* Executable file */
+#define ET_DYN		3		/* Shared object file */
+#define ET_CORE		4		/* Core file */
+#define	ET_NUM		5		/* Number of defined types */
+#define ET_LOPROC	0xff00		/* Processor-specific */
+#define ET_HIPROC	0xffff		/* Processor-specific */
+
+/* Legal values for e_machine (architecture).  */
+
+#define EM_NONE		 0		/* No machine */
+#define EM_M32		 1		/* AT&T WE 32100 */
+#define EM_SPARC	 2		/* SUN SPARC */
+#define EM_386		 3		/* Intel 80386 */
+#define EM_68K		 4		/* Motorola m68k family */
+#define EM_88K		 5		/* Motorola m88k family */
+#define EM_486		 6		/* Intel 80486 */
+#define EM_860		 7		/* Intel 80860 */
+#define EM_MIPS		 8		/* MIPS R3000 big-endian */
+#define EM_S370		 9		/* Amdahl */
+#define EM_MIPS_RS4_BE	10		/* MIPS R4000 big-endian */
+#define EM_RS6000	11		/* RS6000 */
+
+#define EM_PARISC	15		/* HPPA */
+#define EM_nCUBE	16		/* nCUBE */
+#define EM_VPP500	17		/* Fujitsu VPP500 */
+#define EM_SPARC32PLUS	18		/* Sun's "v8plus" */
+#define EM_960		19		/* Intel 80960 */
+#define EM_PPC		20		/* PowerPC */
+
+#define EM_V800		36		/* NEC V800 series */
+#define EM_FR20		37		/* Fujitsu FR20 */
+#define EM_RH32		38		/* TRW RH32 */
+#define EM_MMA		39		/* Fujitsu MMA */
+#define EM_ARM		40		/* ARM */
+#define EM_FAKE_ALPHA	41		/* Digital Alpha */
+#define EM_SH		42		/* Hitachi SH */
+#define EM_SPARCV9	43		/* SPARC v9 64-bit */
+#define EM_TRICORE	44		/* Siemens Tricore */
+#define EM_ARC		45		/* Argonaut RISC Core */
+#define EM_H8_300	46		/* Hitachi H8/300 */
+#define EM_H8_300H	47		/* Hitachi H8/300H */
+#define EM_H8S		48		/* Hitachi H8S */
+#define EM_H8_500	49		/* Hitachi H8/500 */
+#define EM_IA_64	50		/* Intel Merced */
+#define EM_MIPS_X	51		/* Stanford MIPS-X */
+#define EM_COLDFIRE	52		/* Motorola Coldfire */
+#define EM_68HC12	53		/* Motorola M68HC12 */
+#define EM_NUM		54
+
+/* If it is necessary to assign new unofficial EM_* values, please
+   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
+   chances of collision with official or non-GNU unofficial values.  */
+
+#define EM_ALPHA	0x9026
+
+/* Legal values for e_version (version).  */
+
+#define EV_NONE		0		/* Invalid ELF version */
+#define EV_CURRENT	1		/* Current version */
+#define EV_NUM		2
+
+
+/* Program segment header.  */
+
+typedef struct
+{
+  Elf32_Word	p_type;			/* Segment type */
+  Elf32_Off	p_offset;		/* Segment file offset */
+  Elf32_Addr	p_vaddr;		/* Segment virtual address */
+  Elf32_Addr	p_paddr;		/* Segment physical address */
+  Elf32_Word	p_filesz;		/* Segment size in file */
+  Elf32_Word	p_memsz;		/* Segment size in memory */
+  Elf32_Word	p_flags;		/* Segment flags */
+  Elf32_Word	p_align;		/* Segment alignment */
+} Elf32_Phdr;
+
+typedef struct
+{
+  Elf64_Word	p_type;			/* Segment type */
+  Elf64_Word	p_flags;		/* Segment flags */
+  Elf64_Off	p_offset;		/* Segment file offset */
+  Elf64_Addr	p_vaddr;		/* Segment virtual address */
+  Elf64_Addr	p_paddr;		/* Segment physical address */
+  Elf64_Xword	p_filesz;		/* Segment size in file */
+  Elf64_Xword	p_memsz;		/* Segment size in memory */
+  Elf64_Xword	p_align;		/* Segment alignment */
+} Elf64_Phdr;
+
+/* Legal values for p_type (segment type).  */
+
+#define	PT_NULL		0		/* Program header table entry unused */
+#define PT_LOAD		1		/* Loadable program segment */
+#define PT_DYNAMIC	2		/* Dynamic linking information */
+#define PT_INTERP	3		/* Program interpreter */
+#define PT_NOTE		4		/* Auxiliary information */
+#define PT_SHLIB	5		/* Reserved */
+#define PT_PHDR		6		/* Entry for header table itself */
+#define	PT_NUM		7		/* Number of defined types.  */
+#define PT_LOOS		0x60000000	/* Start of OS-specific */
+#define PT_HIOS		0x6fffffff	/* End of OS-specific */
+#define PT_LOPROC	0x70000000	/* Start of processor-specific */
+#define PT_HIPROC	0x7fffffff	/* End of processor-specific */
+
+/* Legal values for p_flags (segment flags).  */
+
+#define PF_X		(1 << 0)	/* Segment is executable */
+#define PF_W		(1 << 1)	/* Segment is writable */
+#define PF_R		(1 << 2)	/* Segment is readable */
+#define PF_MASKPROC	0xf0000000	/* Processor-specific */
+
+
+/* Note section contents.  Each entry in the note section begins with
+   a header of a fixed form.  */
+
+typedef struct
+{
+  Elf32_Word n_namesz;			/* Length of the note's name.  */
+  Elf32_Word n_descsz;			/* Length of the note's descriptor.  */
+  Elf32_Word n_type;			/* Type of the note.  */
+} Elf32_Nhdr;
+
+typedef struct
+{
+  Elf64_Word n_namesz;			/* Length of the note's name.  */
+  Elf64_Word n_descsz;			/* Length of the note's descriptor.  */
+  Elf64_Word n_type;			/* Type of the note.  */
+} Elf64_Nhdr;
+
+/* Known names of notes.  */
+
+/* Solaris entries in the note section have this name.  */
+#define ELF_NOTE_SOLARIS	"SUNW Solaris"
+
+/* Note entries for GNU systems have this name.  */
+#define ELF_NOTE_GNU		"GNU"
+
+
+/* Defined types of notes for Solaris.  */
+
+/* Value of descriptor (one word) is desired pagesize for the binary.  */
+#define ELF_NOTE_PAGESIZE_HINT	1
+
+
+/* Defined note types for GNU systems.  */
+
+/* ABI information.  The descriptor consists of words:
+   word 0: OS descriptor
+   word 1: major version of the ABI
+   word 2: minor version of the ABI
+   word 3: subminor version of the ABI
+*/
+#define ELF_NOTE_ABI		1
+
+/* Known OSes.  These value can appear in word 0 of an ELF_NOTE_ABI
+   note section entry.  */
+#define ELF_NOTE_OS_LINUX	0
+#define ELF_NOTE_OS_GNU		1
+#define ELF_NOTE_OS_SOLARIS2	2
+
+
+/* Motorola 68k specific definitions.  */
+
+/* Intel 80386 specific definitions.  */
+
+/* SUN SPARC specific definitions.  */
+
+/* Values for Elf64_Ehdr.e_flags.  */
+
+#define EF_SPARCV9_MM		3
+#define EF_SPARCV9_TSO		0
+#define EF_SPARCV9_PSO		1
+#define EF_SPARCV9_RMO		2
+#define EF_SPARC_EXT_MASK	0xFFFF00
+#define EF_SPARC_SUN_US1	0x000200
+#define EF_SPARC_HAL_R1		0x000400
+
+/* MIPS R3000 specific definitions.  */
+
+/* Legal values for e_flags field of Elf32_Ehdr.  */
+
+#define EF_MIPS_NOREORDER   1		/* A .noreorder directive was used */
+#define EF_MIPS_PIC	    2		/* Contains PIC code */
+#define EF_MIPS_CPIC	    4		/* Uses PIC calling sequence */
+#define EF_MIPS_XGOT	    8
+#define EF_MIPS_64BIT_WHIRL 16
+#define EF_MIPS_ABI2	    32
+#define EF_MIPS_ABI_ON32    64
+#define EF_MIPS_ARCH	    0xf0000000	/* MIPS architecture level */
+
+/* Legal values for MIPS architecture level.  */
+
+#define EF_MIPS_ARCH_1	    0x00000000	/* -mips1 code.  */
+#define EF_MIPS_ARCH_2	    0x10000000	/* -mips2 code.  */
+#define EF_MIPS_ARCH_3	    0x20000000	/* -mips3 code.  */
+#define EF_MIPS_ARCH_4	    0x30000000	/* -mips4 code.  */
+#define EF_MIPS_ARCH_5	    0x40000000	/* -mips5 code.  */
+
+/* Legal values for p_type field of Elf32_Phdr.  */
+
+#define PT_MIPS_REGINFO	0x70000000	/* Register usage information */
+#define PT_MIPS_RTPROC  0x70000001	/* Runtime procedure table. */
+#define PT_MIPS_OPTIONS 0x70000002
+
+/* Special program header types.  */
+
+#define PF_MIPS_LOCAL	0x10000000
+
+
+/* HPPA specific definitions.  */
+
+/* Legal values for e_flags field of Elf32_Ehdr.  */
+
+#define EF_PARISC_TRAPNL	1	/* Trap nil pointer dereference.  */
+#define EF_PARISC_EXT		2	/* Program uses arch. extensions.  */
+#define EF_PARISC_ARCH		0xffff0000 /* Architecture version.  */
+/* Defined values are:
+				0x020b	PA-RISC 1.0 big-endian
+				0x0210	PA-RISC 1.1 big-endian
+				0x028b	PA-RISC 1.0 little-endian
+				0x0290	PA-RISC 1.1 little-endian
+*/
+
+
+/* Alpha specific definitions.  */
+
+/* Legal values for e_flags field of Elf64_Ehdr.  */
+
+#define EF_ALPHA_32BIT		1	/* All addresses must be < 2GB.  */
+#define EF_ALPHA_CANRELAX	2	/* Relocations for relaxing exist.  */
+
+
+/* PowerPC specific declarations */
+
+/* ARM specific declarations */
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_ARM_RELEXEC     0x01
+#define EF_ARM_HASENTRY    0x02
+#define EF_ARM_INTERWORK   0x04
+#define EF_ARM_APCS_26     0x08
+#define EF_ARM_APCS_FLOAT  0x10
+#define EF_ARM_PIC         0x20
+#define EF_ALIGN8          0x40		/* 8-bit structure alignment is in use */
+#define EF_NEW_ABI         0x80
+#define EF_OLD_ABI         0x100
+
+/* ARM-specific program header flags */
+#define PF_ARM_SB          0x10000000   /* Segment contains the location
+					   addressed by the static base */
+
+#if ELF_CLASS == ELFCLASS32
+typedef Elf32_Ehdr Elf_ehdr;
+typedef Elf32_Phdr Elf_phdr;
+#endif
+
+#if ELF_CLASS == ELFCLASS64
+typedef Elf64_Ehdr Elf_ehdr;
+typedef Elf64_Phdr Elf_phdr;
+#endif
+
+extern int elf_check_arch(Elf_ehdr *ehdr);
+extern void jmp_to_elf_entry(void *entry, void *ube);
+#endif	/* elf.h */
diff --git a/src/include/kmalloc.h b/src/include/kmalloc.h
new file mode 100644
index 0000000000..1884430894
--- /dev/null
+++ b/src/include/kmalloc.h
@@ -0,0 +1,7 @@
+#ifndef KMALLOC_H
+#define KMALLOC_H
+
+#include <stdlib.h>
+#define kmalloc(x,y) malloc(x)
+
+#endif /* KMALLOC_H */
diff --git a/src/include/pci.h b/src/include/pci.h
index e243200bff..23fabf37b6 100644
--- a/src/include/pci.h
+++ b/src/include/pci.h
@@ -14,27 +14,6 @@
  *	PCI System Design Guide
  */
 
-#ifdef EMULATE
-
-// you would not BELIEVE the errors you get if you include stdio.h here
-// since we can build without including it, just SKIP IT
-#if 0
-#undef __NFDBITS
-#undef __FDMASK
-
-#define off_t
-#define ssize_t
-
-#include <stdio.h>
-#include <unistd.h> /* for libc5 */
-
-#endif
-extern void printf(char *format, ...);
-#define printk printf
-#define display(x) printk(x)
-#define printint(x) printf("0x%x", x)
-
-#endif /* EMULATE */
 #ifndef PCI_H
 #define PCI_H
 
@@ -59,7 +38,7 @@ extern void printf(char *format, ...);
 #define PCI_STATUS		0x06	/* 16 bits */
 #define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
 #define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
-#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features */
+#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
 #define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
 #define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
 #define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
@@ -107,7 +86,7 @@ extern void printf(char *format, ...);
 #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
 #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
 #define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
-#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
 #define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
 #define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
 #define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
@@ -156,7 +135,8 @@ extern void printf(char *format, ...);
 #define PCI_PREF_LIMIT_UPPER32	0x2c
 #define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
 #define PCI_IO_LIMIT_UPPER16	0x32
-/* 0x34-0x3b is reserved */
+/* 0x34 same as for htype 0 */
+/* 0x35-0x3b is reserved */
 #define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
 /* 0x3c-0x3d are same as for htype 0 */
 #define PCI_BRIDGE_CONTROL	0x3e
@@ -169,7 +149,8 @@ extern void printf(char *format, ...);
 #define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
 
 /* Header type 2 (CardBus bridges) */
-/* 0x14-0x15 reserved */
+#define PCI_CB_CAPABILITY_LIST	0x14
+/* 0x15 reserved */
 #define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
 #define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
 #define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
@@ -206,10 +187,81 @@ extern void printf(char *format, ...);
 /* 0x48-0x7f reserved */
 
 /* Capability lists */
+
 #define PCI_CAP_LIST_ID		0	/* Capability ID */
 #define  PCI_CAP_ID_PM		0x01	/* Power Management */
 #define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
+#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
+#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
+#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
+#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
 #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
+#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF		4
+
+/* Power Management Registers */
+
+#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
+#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
+#define  PCI_PM_CAP_AUX_POWER	0x0010	/* Auxilliary power support */
+#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
+#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
+#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
+#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
+#define PCI_PM_CTRL		4	/* PM control and status register */
+#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
+#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
+#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
+#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
+#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
+#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
+#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
+#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
+#define PCI_PM_DATA_REGISTER	7	/* (??) */
+#define PCI_PM_SIZEOF		8
+
+/* AGP registers */
+
+#define PCI_AGP_VERSION		2	/* BCD version number */
+#define PCI_AGP_RFU		3	/* Rest of capability flags */
+#define PCI_AGP_STATUS		4	/* Status register */
+#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
+#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
+#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
+#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
+#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
+#define PCI_AGP_COMMAND		8	/* Control register */
+#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
+#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
+#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
+#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
+#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
+#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 4x rate */
+#define PCI_AGP_SIZEOF		12
+
+/* Slot Identification */
+
+#define PCI_SID_ESR		2	/* Expansion Slot Register */
+#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
+#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
+#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
+
+/* Message Signalled Interrupts registers */
+
+#define PCI_MSI_FLAGS		2	/* Various flags */
+#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
+#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
+#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
+#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
+#define PCI_MSI_RFU		3	/* Rest of capability flags */
+#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
+#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
+#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
+#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
 
 /*
  * The PCI interface treats multi-function devices as independent
@@ -377,8 +429,7 @@ void intel_conf_writeb(unsigned long port, unsigned char value);
 unsigned char intel_conf_readb(unsigned long port);
 
 
-#define kmalloc(x, y) malloc(x)
-void *malloc(unsigned int);
+#include <kmalloc.h>
 
 // Rounding for boundaries. 
 // Due to some chip bugs, go ahead and roung IO to 16
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
new file mode 100644
index 0000000000..c86a981f28
--- /dev/null
+++ b/src/include/stdlib.h
@@ -0,0 +1,9 @@
+#ifndef STDLIB_H
+#define STDLIB_H
+
+#include <stddef.h>
+
+extern void *malloc(size_t size);
+void free(void *ptr);
+
+#endif /* STDLIB_H */
diff --git a/src/include/subr.h b/src/include/subr.h
index a24e47c1ca..9a1e101001 100644
--- a/src/include/subr.h
+++ b/src/include/subr.h
@@ -28,12 +28,13 @@ void intel_interrupts_on(void);
 void pc_keyboard_init(void);
 void intel_mainboard_fixup(void);
 unsigned long sizeram(void);
-
+ 
 #ifdef INTEL_PPRO_MTRR
 void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK);
 #endif
 
 #include <pci.h>
+/* FIXME: how should we handle other architectures for pci access here ?? */
 #include <pci-i386.h>
 
 #define PIRQ_SIGNATURE	(('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
diff --git a/src/include/types.h b/src/include/types.h
index 829aa597f9..4b9dadfe55 100644
--- a/src/include/types.h
+++ b/src/include/types.h
@@ -1,8 +1,18 @@
 #ifndef TYPES_H
 #define TYPES_H
-typedef unsigned char u8;
-typedef unsigned short u16;
-typedef unsigned long u32;
-typedef unsigned long size_t;
-#define NULL (0)
+
+#include <stdint.h>
+#include <stddef.h>
+
+typedef uint8_t  u8;
+typedef int8_t   s8;
+typedef uint16_t u16;
+typedef int16_t  s16;
+typedef uint32_t u32;
+typedef int32_t  s32;
+typedef uint64_t u64;
+typedef int64_t  s64;
+
+/* FIXME is BITS_PER_LONG needed? */
+
 #endif
diff --git a/src/lib/definitions.h b/src/lib/definitions.h
index 3786632d41..0baef9bbf8 100644
--- a/src/lib/definitions.h
+++ b/src/lib/definitions.h
@@ -1,35 +1,9 @@
-/* Comment this out unless you are debugging under linux */
-#define EMULATE
-#undef EMULATE
+#ifndef DEFINITIONS_H
+#define DEFINITIONS_H
 
-#ifdef EMULATE
-#include <unistd.h>
-#else
-typedef unsigned long size_t;
-#endif
 
-#ifdef EMULATE
-  #define MEMSIZE 2*1024*1024       /* Make a 2MB fake memory space */
-  char memimage[MEMSIZE];          /* Make a 2MB fake memory space */
-#else
-  #define memimage 0x0            /* Ignore memimage */
-#endif
+#include <stddef.h>
 
-#define KERNEL_START  (0x100000 + memimage) /* Put our copy of linux here   */
-
-#if 0
-#define ZIP_START     (0x30000  + memimage) /* The zip file starts here     */
-#define ZIP_SIZE      262164                /* linux.gz size (we ought to   */
-#endif
-
-/* with flash, it's a bunch of 64k segments. */
-#define ZIP_START (0xfff40000)
-#define ZIP_SIZE (0x10000)
-
-#ifdef EMULATE
-char input_array[0x100000];
-#undef ZIP_START
-#define ZIP_START (input_array + 0x40000)
-#endif
-                                            /*   make this dynamic)         */
+#define KERNEL_START  (0x100000) /* Put our copy of linux here   */
 
+#endif /* DEFINITIONS_H */
diff --git a/src/lib/linuxbiosmain.c b/src/lib/linuxbiosmain.c
index 82fef17cc3..b9636bf4d3 100644
--- a/src/lib/linuxbiosmain.c
+++ b/src/lib/linuxbiosmain.c
@@ -20,8 +20,7 @@
 #include "definitions.h"
 #include "printk.h"
 #include <params.h>
-
-extern void intel_post(char value);
+#include <subr.h>
 
 #define ERRCHK
 #undef TRACEV
@@ -46,7 +45,11 @@ typedef unsigned long ulg;
 #define WSIZE 0x8000		/* Window size must be at least 32k, and a power of two */
 
 uch *inbuf;			/* input buffer */
+#if 0
 static uch window[WSIZE];	/* Sliding window buffer */
+#else
+static uch *window;		/* Sliding window buffer */
+#endif
 
 unsigned insize;		/* valid bytes in inbuf */
 unsigned inptr;			/* index of next byte to be processed in inbuf */
@@ -69,7 +72,7 @@ typedef void (*kernel) ();
 kernel v;
 
 void malloc_init(unsigned long start, unsigned long end);
-void *malloc(int size);
+void *malloc(size_t size);
 
 static void flush_window(void);
 static void free(void *where);
@@ -1331,7 +1334,7 @@ void malloc_init(unsigned long start, unsigned long end)
 	free_mem_end_ptr = end;
 }
 
-void *malloc(int size)
+void *malloc(size_t size)
 {
 	void *p;
 
@@ -1392,6 +1395,7 @@ void *memcpy(void *__dest, __const void *__src, size_t __n)
 	return __dest;
 }
 
+
 /* ===========================================================================
  * Write the output window window[0..outcnt-1] and update crc and bytes_out.
  * (Used for the decompressed data only.)
@@ -1422,69 +1426,149 @@ void setup_output_buffer()
 	DBG("output data is 0x%08x\n", (unsigned long) output_data);
 }
 
-/* TODO: this must move to chip/intel */
-/* we have to do more than we thought. I assumed Linux would do all the
- * interesting parts, and I was wrong. 
- */
-struct ioapicreg {
-	unsigned int reg;
-	unsigned int value;
-};
+#if USE_ELF_BOOT
+#include <boot/elf.h>
+#include <boot/uniform_boot.h>
 
-struct ioapicreg ioapicregvalues[] = {
-	{0x10, 0x10000}, {0x11, 0x0},
-	{0x12, 0x959}, {0x13, 0xff000000},
-	{0x14, 0x951}, {0x15, 0xff000000},
-	{0x16, 0x961}, {0x17, 0x0},
-	{0x18, 0x969}, {0x19, 0xff000000},
-	{0x1a, 0x971}, {0x1b, 0x0},
-	{0x1c, 0x979}, {0x1d, 0x0},
-	{0x1e, 0x981}, {0x1f, 0x0},
-	{0x20, 0x989}, {0x21, 0xff000000},
-	{0x22, 0x10000}, {0x23, 0x0},
-	{0x24, 0x10000}, {0x25, 0x0},
-	{0x26, 0x10000}, {0x27, 0x0},
-	{0x28, 0x991}, {0x29, 0xff000000},
-	{0x2a, 0x10000}, {0x2b, 0x0},
-	{0x2c, 0x999}, {0x2d, 0x0},
-	{0x2e, 0x9a1}, {0x2f, 0x0},
-	{0x30, 0x10000}, {0x31, 0x0},
-	{0x32, 0x10000}, {0x33, 0x0},
-	{0x34, 0x10000}, {0x35, 0x0},
-	{0x36, 0xa9a9}, {0x37, 0xff000000},
-	{0x38, 0x10000}, {0x39, 0x0},
-	{0x3a, 0xa9b1}, {0x3b, 0xff000000},
-	{0x3c, 0x10000}, {0x3d, 0x0},
-	{0x3e, 0x10000}, {0x3f, 0x0}
-};
-
-void setup_apic()
+static int elfboot(unsigned long totalram)
 {
+	static unsigned char header[ELF_HEAD_SIZE];
+	unsigned long offset;
+	Elf_ehdr *ehdr;
+	Elf_phdr *phdr;
+	void *ptr, *entry;
 	int i;
-	unsigned long l1;
-	unsigned long nvram = 0xfec00000;
-	volatile unsigned long *l;
-	struct ioapicreg *a = ioapicregvalues;
 
-	l = (unsigned long *) nvram;
-	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
-	     i++, a++) {
-		*l = a->reg;
-		l[4] = a->value;
-		l1 = l[4];
-		if ((i==0) && (l1 == 0xffffffff)) {
-			DBG("IO APIC not responding.\n");
-			return;
-		}
-		DBG("for IRQ, reg 0x%08x value 0x%08x\n", a->reg, l1);
+	printk("\n");
+	printk("Welcome to elfboot, the open sourced starter.\n");
+	printk("Febuary 2001, Eric Biederman.\n");
+	printk("Version 0.99\n");
+	printk("\n");
+	ptr = get_ube_pointer(totalram);
+
+	intel_post(0xf8);
+	/* Read in the initial 512 bytes */
+	for(offset = 0; offset < 512; offset++) {
+		header[offset] = get_byte();
 	}
+	ehdr = (Elf_ehdr *)(&header[0]);
+	entry = (void *)(ehdr->e_entry);
+	
+	/* Sanity check the elf header */
+	if ((memcmp(ehdr->e_ident, ELFMAG, 4) != 0) ||
+		(ehdr->e_type != ET_EXEC) ||
+		(!elf_check_arch(ehdr)) ||
+		(ehdr->e_ident[EI_VERSION] != EV_CURRENT) ||
+		(ehdr->e_version != EV_CURRENT) ||
+		(ehdr->e_phoff > ELF_HEAD_SIZE) ||
+		(ehdr->e_phentsize != sizeof(Elf_phdr)) ||
+		((ehdr->e_phoff + (ehdr->e_phentsize * ehdr->e_phnum)) > 
+			ELF_HEAD_SIZE)) {
+		goto out;
+	}
+
+	phdr = (Elf_phdr *)&header[ehdr->e_phoff];
+	offset = 0;
+	while(1) {
+		Elf_phdr *cur_phdr = 0;
+		int i,len;
+		unsigned long start_offset;
+		unsigned char *dest, *middle, *end;
+		/* Find the program header that descibes the current piece
+		 * of the file.
+		 */
+		for(i = 0; i < ehdr->e_phnum; i++) {
+			if (phdr[i].p_type != PT_LOAD) {
+				continue;
+			}
+			if (phdr[i].p_filesz > phdr[i].p_memsz) {
+				continue;
+			}
+			if (phdr[i].p_offset >= offset) {
+				if (!cur_phdr ||
+					(cur_phdr->p_offset > phdr[i].p_offset)) {
+					cur_phdr = &phdr[i];
+				}
+			}
+		}
+		/* If we are out of sections we are done */
+		if (!cur_phdr) {
+			break;
+		}
+		printk("Loading Section: addr: 0x%08x memsz: 0x%08x filesz: 0x%08x\n",
+			cur_phdr->p_paddr, cur_phdr->p_memsz, cur_phdr->p_filesz);
+
+		/* Compute the boundaries of the section */
+		dest = (unsigned char *)(cur_phdr->p_paddr);
+		end = dest + cur_phdr->p_memsz;
+		len = cur_phdr->p_filesz;
+		if (len > cur_phdr->p_memsz) {
+			len = cur_phdr->p_memsz;
+		}
+		middle = dest + len;
+		start_offset = cur_phdr->p_offset;
+
+		/* Skip intial buffer unused bytes */
+		if (offset < ELF_HEAD_SIZE) {
+			if (start_offset < ELF_HEAD_SIZE) {
+				offset = start_offset;
+			} else {
+				offset = ELF_HEAD_SIZE;
+			}
+		}
+
+		/* Skip the unused bytes */
+		while(offset < start_offset) {
+			offset++;
+			get_byte();
+		}
+
+		/* Copy data from the initial buffer */
+		if (offset < ELF_HEAD_SIZE) {
+			size_t len;
+			if ((cur_phdr->p_filesz + start_offset) > ELF_HEAD_SIZE) {
+				len = ELF_HEAD_SIZE - start_offset;
+			}
+			else {
+				len = cur_phdr->p_filesz;
+			}
+			memcpy(dest, &header[start_offset], len);
+			dest += len;
+		}
+		
+		/* Read the section into memory */
+		while(dest < middle) {
+			*(dest++) = get_byte();
+		}
+		offset += cur_phdr->p_filesz;
+		/* Zero the extra bytes */
+		while(dest < end) {
+			*(dest++) = 0;
+		}
+	}
+
+	DBG("Jumping to boot code\n");
+	intel_post(0xfe);
+
+	/* Jump to kernel */
+	jmp_to_elf_entry(entry, ptr);
+
+ out:
+	printk("Bad ELF Image\n");
+	for(i = 0; i < sizeof(*ehdr); i++) {
+		if ((i & 0xf) == 0) {
+			printk("\n");
+		}
+		printk("%02x ", header[i]);
+	}
+	printk("\n");
+
+	return 0;
 }
+#endif
 
-unsigned char *zkernel_start;
-unsigned long zkernel_mask;
 
-int
-linuxbiosmain(unsigned long base, unsigned long totalram)
+int linuxbiosmain(unsigned long base, unsigned long totalram)
 {
 	unsigned char *empty_zero_page;
 	extern int firstfill;
@@ -1500,6 +1584,11 @@ linuxbiosmain(unsigned long base, unsigned long totalram)
 	bytes_out = 0;
 	output_ptr = 0;
 
+
+#if USE_ELF_BOOT
+	return elfboot(totalram);
+#else
+
 	printk("\n");
 	printk("Welcome to start32, the open sourced starter.\n");
 	printk("This space will eventually hold more diagnostic information.\n");
@@ -1516,18 +1605,6 @@ linuxbiosmain(unsigned long base, unsigned long totalram)
 	cmd_line = "root=/dev/hda1 single";
 #endif
 
-#ifdef ZKERNEL_START
-	zkernel_start = (unsigned char *)ZKERNEL_START;
-#else
-	zkernel_start = (unsigned char *)0xfff80000;
-#endif
-
-#ifdef ZKERNEL_MASK
-	zkernel_mask = ZKERNEL_MASK;
-#else
-	zkernel_mask = 0x0000ffff;
-#endif
-
 #ifdef LOADER_SETUP
 	loader_setup(base,
 		     totalram,
@@ -1538,6 +1615,7 @@ linuxbiosmain(unsigned long base, unsigned long totalram)
 		     &zkernel_mask);
 #endif
 
+	window = malloc(WSIZE);
 	setup_output_buffer();
 
 	DBG("Making CRC\n");
@@ -1576,10 +1654,6 @@ linuxbiosmain(unsigned long base, unsigned long totalram)
 	set_display(empty_zero_page, 25, 80);
 	set_initrd(empty_zero_page, initrd_start, initrd_size);
 
-	/* set up the IO-APIC for the clock interrupt. */
-	/* this needs to move to intel_main.c at some point. */
-	setup_apic();
-	intel_post(0xfc);
 
 	DBG("Jumping to boot code\n");
 	intel_post(0xfe);
@@ -1603,4 +1677,5 @@ linuxbiosmain(unsigned long base, unsigned long totalram)
 			     :: "i" (0x100000));
 
 	return 0;		/* It should not ever return */
+#endif
 }
diff --git a/src/lib/memcmp.c b/src/lib/memcmp.c
new file mode 100644
index 0000000000..46f13a41bd
--- /dev/null
+++ b/src/lib/memcmp.c
@@ -0,0 +1,17 @@
+#include <string.h>
+
+int memcmp(const void *src1, const void *src2, size_t bytes)
+{
+	const unsigned char *s1, *s2;
+	int result;
+	s1 = src1;
+	s2 = src2;
+	result = 0;
+	while((bytes > 0) && (result == 0)) {
+		result = *s1 - *s2;
+		bytes--;
+		s1++;
+		s2++;
+	}
+	return result;
+}
diff --git a/src/lib/memcpy.c b/src/lib/memcpy.c
new file mode 100644
index 0000000000..ad8e8bd3f0
--- /dev/null
+++ b/src/lib/memcpy.c
@@ -0,0 +1,11 @@
+#include <string.h>
+void *memcpy(void *__dest, __const void *__src, size_t __n)
+{
+	int i;
+	char *d = (char *) __dest, *s = (char *) __src;
+
+	for (i = 0; i < __n; i++)
+		d[i] = s[i];
+
+	return __dest;
+}
diff --git a/src/lib/memset.c b/src/lib/memset.c
new file mode 100644
index 0000000000..c1bb4f841f
--- /dev/null
+++ b/src/lib/memset.c
@@ -0,0 +1,12 @@
+#include <string.h>
+
+void *memset(void *s, int c, size_t n)
+{
+	int i;
+	char *ss = (char *) s;
+
+	for (i = 0; i < n; i++)
+		ss[i] = c;
+
+	return s;
+}
diff --git a/src/northbridge/acer/m1631/chipset_init.inc b/src/northbridge/acer/m1631/chipset_init.inc
index 58dea2aa14..6e43fe848f 100644
--- a/src/northbridge/acer/m1631/chipset_init.inc
+++ b/src/northbridge/acer/m1631/chipset_init.inc
@@ -75,6 +75,12 @@ register_table:
 	.byte 0x60,~0x20, 0x00
 	.byte 0xfb, 0x00, 0x31
 	.byte 0x0 /* end of table */
+
+m1535_table:
+	.byte 0x44, 0x00, 0x5d	// set edge mode, primary channel IRQ 14
+	.byte 0x75, 0x00, 0x0f	// secondary channel 15
+	.byte 0x58, 0x00, 0x4c	// enable IDE controller
+	.byte 0x0 // end of m1535_table 
 chipsetinit_start:
 
 	mov	$0x3f0, %edx
@@ -116,3 +122,23 @@ chipsetinit_start:
 	jmp 1b
 
 done_chipset_init:
+m1535_init:
+	movl	$m1535_table, %esi
+1: 
+	xorl	%edx, %edx
+	movl	$0x00003800, %eax	// southbridge is dev 7 << 3 = 0x38
+	movb	(%esi), %cl /* save the address in %cl */
+	movb	%cl, 	%al
+	testb 	%al, %al
+	jz	done_m1535_init
+	PCI_READ_CONFIG_BYTE
+	movb	%al, %dl
+	inc	%esi
+	andb	(%esi), %dl
+	inc %esi
+	orb	(%esi), %dl
+	mov	%cl, %al
+	PCI_WRITE_CONFIG_BYTE
+	inc %esi
+	jmp 1b
+done_m1535_init:
diff --git a/util/config/NLBConfig.py b/util/config/NLBConfig.py
index 09f9ea7606..36c95eb1cb 100644
--- a/util/config/NLBConfig.py
+++ b/util/config/NLBConfig.py
@@ -43,7 +43,7 @@ def addobject(object, sourcepath, rule):
 # make won't apply the .c.o rule. Toy!
 
 def addobject_defaultrule(object, sourcepath):
-	defaultrule = "\t cc -c $(CFLAGS) $(CPUFLAGS) $<"
+	defaultrule = "\t $(CC) -c $(CFLAGS) $<"
 	objectrules.append([object, sourcepath, defaultrule])
 
 # for all these functions, you need:
@@ -67,10 +67,7 @@ def target(dir, targ_name):
 		print ' then run this program again'
 		sys.exit(1)
 
-def handleconfig(dir, type, name):
-	# seems weird, eh? but config file are always done from
-	# treetop
-	dir = os.path.join(treetop, type, name)
+def handleconfig(dir):
 	file = os.path.join(dir, 'Config')
 	print "Process config file: ", file
 	if os.path.isfile(file):
@@ -86,9 +83,25 @@ def buildfullpath(type, name):
 
 def common_command_action(dir, type, name):
 	fullpath = buildfullpath(type, name)
-	handleconfig(dir, 'src', fullpath)
+	realpath = os.path.join('src', fullpath)
+	# seems weird, eh? but config file are always done from
+	# treetop
+	realpath = os.path.join(treetop, realpath)
+	handleconfig(realpath)
 	return fullpath
 
+def dir(base_dir, name):
+	regexp = re.compile(r"^/(.*)")
+	m = regexp.match(name)
+	if m and m.group(1):
+		# /dir
+		fullpath = os.path.join("src", m.group(1))
+		fullpath = os.path.join(treetop, fullpath)
+	else:
+		# dir
+		fullpath = os.path.join(base_dir, name)
+	handleconfig(fullpath)
+
 def mainboard(dir, mainboard_name):
 	common_command_action(dir, 'mainboard', mainboard_name)
 
@@ -145,11 +158,14 @@ def makerule(dir, rule):
 	rest = "(.*)"
 	w = "[" + wspc + "]*"
 	cmd = "([^" + wspc + "]*)"
-	namepat = "(.*)"
+	namepat = "([^;]*)"
 	pat = cmd  + w + ":" + w + namepat + w + ";" + w + rest + w
 	#	print "pat :", pat, ":", rule
 	command_re = re.compile(pat)
 	m = command_re.match(rule)
+	if (not m):
+		print "\nBadly formed rule: ", rule, "\n"
+		sys.exit()
 	rulename = m.group(1)
 	dependencies = m.group(2)
 	actions = m.group(3)
@@ -171,7 +187,8 @@ def addaction(dir, rule):
         rulename = m.group(1)
         actions = m.group(2)
         # print "rulename :", rulename
-        # print "    actions ", actions
+        # print "    actions ", actions, "\n"
+	# print "rules[rulename]=", makebaserules[rulename], "\n"
         makebaserules[rulename].append(actions)
 	
 # add a dependency
@@ -254,7 +271,7 @@ command_vals = {
 	'pcibridge'   : [],   # vendor, bridgename
 	'superio'     : [],   # vendor, superio name
 	'object'      : {},   # path/filename.[cS]
-	'raminit'     : []    # set of files to include for ram init
+	'raminit'     : [],   # set of files to include for ram init
 	}
 
 command_actions = {
@@ -270,6 +287,7 @@ command_actions = {
 	'object'      : object,
 	'linux'       : linux,
 	'raminit'     : raminit,
+	'dir'         : dir,
 	'keyboard'    : keyboard, 
 	'docipl'      : docipl,
 	'makedefine'    : makedefine,
@@ -473,21 +491,15 @@ treetop = command_vals['TOP']
 makebase = os.path.join(treetop, "util/config/make.base")
 crt0base = os.path.join(treetop, "util/config/p5crt0.base")
 ldscriptbase = os.path.join(treetop, "util/config/ldscript.base")
-doconfigfile(treetop, sys.argv[1])
-
-
-# do standard config files that the user need not specify
-# for now, this is just 'lib', but it may be more later. 
-libdir = treetop + "/src/lib"
-libconfigfile = libdir + "/Config"
-print "Process config file: ", libconfigfile
-doconfigfile(libdir, libconfigfile)
 
 # now read in the base files. 
 print "Now Process the base files"
 print "Makebase is :", makebase, ":"
 doconfigfile(treetop, makebase)
 
+# now read in the customizing script
+doconfigfile(treetop, sys.argv[1])
+
 # print out command values
 #print "Command Values:"
 #for key,val in command_vals.items():