From 215cf2d9abccc855bc7cd27b29f6ed241bca55fe Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 27 Jan 2025 14:47:12 -0700 Subject: [PATCH] soc/intel/alderlake/romstage: Update UFS disable sequence Currently after UFS is disabled, if the device is coming out of S5 sleep state then a warm reset is triggered such that PMC samples the UFS function disable bit and disables the UFS controller accordingly. Sometimes during the boot flow, an additional kind of reset gets triggered - Power cycle Reset through CMoff. Hence initiate a warm reset when the host comes out of S5 sleep state or Power cycle Reset through CMoff. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Ensure that when the device switches from normal mode to developer mode an extra warm reset is triggered such that the UFS controller is disabled. Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/86170 Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) Reviewed-by: Dinesh Gehlot --- src/soc/intel/alderlake/romstage/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index daf2b76ae6..b1ac1caefa 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -197,7 +197,8 @@ void mainboard_romstage_entry(void) /* Program to Disable UFS Controllers */ if (!is_devfn_enabled(PCH_DEVFN_UFS) && (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) { - if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) { + if ((ps->prev_sleep_state == ACPI_S5 || cse_check_host_cold_reset()) && + !mainboard_expects_another_reset()) { printk(BIOS_INFO, "Disabling UFS controllers\n"); disable_ufs(); printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n");