mtrr fixes for 630, they are a hack now.
ipl.S: check for FRAMEBUFFER, don't set 0x63 if HAVE_FRAMEBUFFER not defined. Starting support for L440GX
This commit is contained in:
Ronald G. Minnich
parent
8d01b04558
commit
21322ba3b7
6 changed files with 260 additions and 4 deletions
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@ -11,7 +11,7 @@ CPUFLAGS += -DUSE_DOC_MIL
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CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
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CPUFLAGS += -DRAMTEST
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CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DCMD_LINE='"root=/dev/nftla1 single console=ttyS0,115200 mem=64m "'
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CPUFLAGS += -DCMD_LINE='"root=/dev/nftla1 single console=ttyS0,115200 "'
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LINUX=$(TOP)/../linux-2.4.0-test6.sis
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28
src/cpu/p5/tsc.c
Normal file
28
src/cpu/p5/tsc.c
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@ -0,0 +1,28 @@
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#define rdtsc(low,high) \
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__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
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static void __rdtsc_delay(unsigned long loops)
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{
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unsigned long bclock, now;
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rdtscl(bclock);
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do
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{
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rdtscl(now);
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}
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while((now-bclock) < loops);
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}
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static void __rdtsc_delay2(unsigned long loops, unsigned pm_io)
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{
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unsigned long bclock, now;
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rdtscl(bclock);
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do
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{
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outl((1 << 11) | ( 1 << 8), pm_io + 0x00);
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rdtscl(now);
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}
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while((now-bclock) < loops);
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}
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@ -27,6 +27,7 @@
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#include <cpu/p6/msr.h>
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#include <cpu/p6/mtrr.h>
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#include <printk.h>
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#define arraysize(x) (sizeof(x)/sizeof((x)[0]))
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@ -155,8 +156,42 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK)
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{
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#ifdef SIS630
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/* hardcoded for 128MB SDRAM, 4 MB SMA */
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intel_set_var_mtrr(0, 0, 128 * 1024 * 1024, MTRR_TYPE_WRBACK);
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intel_set_var_mtrr(1, 124 * 1024 * 1024, 4 * 1024 * 1024, MTRR_TYPE_UNCACHABLE);
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// change this 10/29/00 RGM
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// set WRBACk to the size of ram, and SMA to the last 4M
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// This works because Ollie fixed Dram setup with SPD
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// coming in, from sis sizeram, the size is size of ram -
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// 256M. We should probably change the way this is done.
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// For now, take ramsizeK, add 4M, that's it.
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// you have to round up the ramsize because MTRRs
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// have to be on a power of two boundary.
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// BUT: UC and WB types are allowed to overlap.
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// so there is no problem with letting MTRR 0 overlap MTRR 1
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printk(KERN_INFO "set_mtrr: rambase is 0x%x, ramsizeK is 0x%x\n",
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rambase, ramsizeK);
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#if 0
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// why doesn't this work! machine hangs!
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printk(KERN_INFO "setting MTRR 0 size to 0x%x\n",
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(ramsizeK + 4096) * 1024);
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intel_set_var_mtrr(0, 0, (ramsizeK + 4096) * 1024, MTRR_TYPE_WRBACK);
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intel_set_var_mtrr(1, (ramsizeK * 1024),
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4096 * 1024, MTRR_TYPE_UNCACHABLE);
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#else
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// Ollie, this is a hack! Sorry! Ron
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printk(KERN_INFO "Setting 256M MTRR 0\n");
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intel_set_var_mtrr(0, 0, 256 * 1024 * 1024, MTRR_TYPE_WRBACK);
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#ifdef HAVE_FRAMEBUFFER
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// for SiS, ramsizeK is the base of the framebuffer.
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// but if it's less than 60M, don't bother ...
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if (ramsizeK > 60*1024)
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{
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printk(KERN_INFO "Setting %dM, 4M size MTRR 1\n",
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ramsizeK);
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intel_set_var_mtrr(1, ramsizeK * 1024, 4096 * 1024,
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MTRR_TYPE_UNCACHABLE);
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}
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#endif
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printk(KERN_INFO "MTRRs set\n");
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#endif
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#else
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printk("Setting variable MTRR 0 to %dK\n", ramsizeK);
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intel_set_var_mtrr(0, 0, ramsizeK * 1024, MTRR_TYPE_WRBACK);
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179
src/mainboard/intel/l440gx/mainboard.c
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179
src/mainboard/intel/l440gx/mainboard.c
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@ -0,0 +1,179 @@
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#include <printk.h>
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#include <pci.h>
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// this needs to be moved about a bit to northbridge.c etc.
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void intel_mainboard_fixup()
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{
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struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev;
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unsigned smbus_io, pm_io;
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unsigned int i, j;
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printk("intel_mainboard_fixup()\n");
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#if 1
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pm_pcidev = pci_find_device(0x8086, 0x7113, 0);
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nic_pcidev = pci_find_device(0x8086, 0x1229, 0);
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host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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#endif
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#if 1
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pci_write_config_byte(nic_pcidev, 0x3c, 21);
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#endif
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#if 1
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{
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unsigned char byte;
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unsigned short word;
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unsigned long dword;
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for(i = 0; i < 8; i++) {
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pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte);
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printk("DRB[i] = 0x%02x\n", byte);
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}
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pci_read_config_byte(host_bridge_pcidev, 0x57, &byte);
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printk("DRAMC = 0x%02x\n", byte);
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pci_read_config_byte(host_bridge_pcidev, 0x74, &byte);
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printk("RPS = 0x%02x\n", byte);
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pci_read_config_word(host_bridge_pcidev, 0x78, &word);
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printk("PGPOL = 0x%04x\n", word);
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pci_read_config_dword(host_bridge_pcidev, 0x50, &dword);
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printk("NBXCFG = 0x%04x\n", dword);
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}
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#endif
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#if 1
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printk("Reset Control Register\n");
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outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9);
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printk("port 92\n");
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outb((inb(0x92) & 0xFE), 0x92);
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printk("Disable Nmi\n");
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outb(0, 0x70);
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printk("enabling smbus\n");
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#if 0
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smbus_io = NewPciIo(0x10);
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#else
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smbus_io = 0xFFF0;
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#endif
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pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */
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pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */
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pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */
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printk("enable pm functions\n");
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#if 0
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pm_io = NewPciIo(0x40);
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#else
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pm_io = 0xFF80;
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#endif
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pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */
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pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */
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printk("disabling smi\n");
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/* GLBEN */
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outw(0x00, pm_io + 0x20);
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/* GLBCTL */
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outl((1 << 24), pm_io + 0x28);
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printk("Disable more pm stuff\n");
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/* PMEN */
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outw((1 << 8), pm_io + 0x02);
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/* PMCNTRL */
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outw((0x5 << 10) , pm_io + 0x4);
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/* PMTMR */
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outl(0, pm_io + 0x08);
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/* GPEN */
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outw(0, pm_io + 0x0e);
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/* PCNTRL */
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outl(0, pm_io + 0x10);
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/* GLBSTS */
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/* DEVSTS */
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/* GLBEN see above */
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/* GLBCTL see above */
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/* DEVCTL */
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outl(0, pm_io + 0x2c);
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/* GPIREG */
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/* GPOREG */
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printk("Set the subsystem vendor id\n");
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pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086);
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printk("Disabling pm stuff in pci config space\n");
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#define MAX_COUNTERS
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#ifndef MAX_COUNTERS
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/* counters to 0 */
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#define WHICH_COUNTERS(min,max) min
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#else
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/* max out the counters */
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#define WHICH_COUNTERS(min,max) max
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#endif
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/* CNTA */
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pci_write_config_dword(pm_pcidev, 0x44, WHICH_COUNTERS(0x004000f0, 0xFFFFFFFF));
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/* CNTB */
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pci_write_config_dword(pm_pcidev, 0x48, WHICH_COUNTERS(0x00000400, 0x007c07df));
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/* GPICTL */
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pci_write_config_dword(pm_pcidev, 0x4c, 0);
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/* DEVRESD */
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pci_write_config_dword(pm_pcidev, 0x50, 0);
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/* DEVACTA */
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pci_write_config_dword(pm_pcidev, 0x54, 0);
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/* DEVACTB */
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pci_write_config_dword(pm_pcidev, 0x58, 0);
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/* DEVRESA */
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pci_write_config_dword(pm_pcidev, 0x5c, 0);
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/* DEVRESB */
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pci_write_config_dword(pm_pcidev, 0x60, 0);
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/* DEVRESC */
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pci_write_config_dword(pm_pcidev, 0x64, 0); /* might kill the serial port */
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/* DEVRESE */
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pci_write_config_dword(pm_pcidev, 0x68, 0);
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/* DEVRESF */
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pci_write_config_dword(pm_pcidev, 0x6c, 0);
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/* DEVRESG */
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pci_write_config_dword(pm_pcidev, 0x70, 0);
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/* DEVRESH */
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pci_write_config_dword(pm_pcidev, 0x74, 0);
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/* DEVRESI */
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pci_write_config_dword(pm_pcidev, 0x78, 0);
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/* DEVRESJ */
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pci_write_config_dword(pm_pcidev, 0x7c, 0);
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#endif
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#if 1
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/* Verify that smi is disabled */
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printk("Testing SMI\r\n");
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{
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u32 value;
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pci_read_config_dword(pm_pcidev, 0x58, &value);
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pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25));
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}
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outb(inb(0xb2), 0xb2);
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printk("SMI disabled\r\n");
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#endif
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#if 0
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for(i = 0; i < 255; i++) {
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printk("%08x\r\n", i);
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__rdtsc_delay2(1000000000UL, pm_io);
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}
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#endif
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}
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@ -164,11 +164,17 @@ no_sdram:
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movw %fs, %ax
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movb $0x63, %ah
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#ifdef HAVE_FRAMEBUFFER
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orb $0x90, %al # enable SMA 4 MB for VGA
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#endif
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#else /* SIZE_ALL */
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no_sdram:
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#ifdef HAVE_FRAMEBUFFER
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# enable DIMM 0 and
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movw $0x6391, %ax # enable SMA 4 MB for VGA
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#else
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movw $0x6301, %ax # enable DIMM 0
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#endif // HAVE_FRAMEBUFFER
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#endif /* SIZE_ALL */
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CALL_SP(write_pci_register) # write register 0x63
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8
src/southbridge/intel/piix4e/southbridge.c
Normal file
8
src/southbridge/intel/piix4e/southbridge.c
Normal file
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@ -0,0 +1,8 @@
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#include <pci.h>
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#include <pc80/keyboard.h>
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#include <printk.h>
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void
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southbridge_fixup()
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{
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}
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