From 21322ba3b7459d4ead2103b67089d7c5c26cf455 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 1 Nov 2000 03:08:35 +0000 Subject: [PATCH] mtrr fixes for 630, they are a hack now. ipl.S: check for FRAMEBUFFER, don't set 0x63 if HAVE_FRAMEBUFFER not defined. Starting support for L440GX --- romimages/MS7308E_FLASHROOT/Makefile | 2 +- src/cpu/p5/tsc.c | 28 ++++ src/cpu/p6/mtrr.c | 39 ++++- src/mainboard/intel/l440gx/mainboard.c | 179 +++++++++++++++++++++ src/northsouthbridge/sis/630/ipl.S | 8 +- src/southbridge/intel/piix4e/southbridge.c | 8 + 6 files changed, 260 insertions(+), 4 deletions(-) create mode 100644 src/cpu/p5/tsc.c create mode 100644 src/mainboard/intel/l440gx/mainboard.c create mode 100644 src/southbridge/intel/piix4e/southbridge.c diff --git a/romimages/MS7308E_FLASHROOT/Makefile b/romimages/MS7308E_FLASHROOT/Makefile index 2e3d9ff4ad..3cf8369b03 100644 --- a/romimages/MS7308E_FLASHROOT/Makefile +++ b/romimages/MS7308E_FLASHROOT/Makefile @@ -11,7 +11,7 @@ CPUFLAGS += -DUSE_DOC_MIL CPUFLAGS += -DFINAL_MAINBOARD_FIXUP CPUFLAGS += -DRAMTEST CPUFLAGS += -DSERIAL_CONSOLE -CPUFLAGS += -DCMD_LINE='"root=/dev/nftla1 single console=ttyS0,115200 mem=64m "' +CPUFLAGS += -DCMD_LINE='"root=/dev/nftla1 single console=ttyS0,115200 "' LINUX=$(TOP)/../linux-2.4.0-test6.sis diff --git a/src/cpu/p5/tsc.c b/src/cpu/p5/tsc.c new file mode 100644 index 0000000000..acacfd0109 --- /dev/null +++ b/src/cpu/p5/tsc.c @@ -0,0 +1,28 @@ +#define rdtsc(low,high) \ + __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) + +static void __rdtsc_delay(unsigned long loops) +{ + unsigned long bclock, now; + + rdtscl(bclock); + do + { + rdtscl(now); + } + while((now-bclock) < loops); +} + +static void __rdtsc_delay2(unsigned long loops, unsigned pm_io) +{ + unsigned long bclock, now; + + rdtscl(bclock); + do + { + outl((1 << 11) | ( 1 << 8), pm_io + 0x00); + rdtscl(now); + } + while((now-bclock) < loops); +} + diff --git a/src/cpu/p6/mtrr.c b/src/cpu/p6/mtrr.c index 0376adc07f..1a97216062 100644 --- a/src/cpu/p6/mtrr.c +++ b/src/cpu/p6/mtrr.c @@ -27,6 +27,7 @@ #include #include +#include #define arraysize(x) (sizeof(x)/sizeof((x)[0])) @@ -155,8 +156,42 @@ void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK) { #ifdef SIS630 /* hardcoded for 128MB SDRAM, 4 MB SMA */ - intel_set_var_mtrr(0, 0, 128 * 1024 * 1024, MTRR_TYPE_WRBACK); - intel_set_var_mtrr(1, 124 * 1024 * 1024, 4 * 1024 * 1024, MTRR_TYPE_UNCACHABLE); + // change this 10/29/00 RGM + // set WRBACk to the size of ram, and SMA to the last 4M + // This works because Ollie fixed Dram setup with SPD + // coming in, from sis sizeram, the size is size of ram - + // 256M. We should probably change the way this is done. + // For now, take ramsizeK, add 4M, that's it. + // you have to round up the ramsize because MTRRs + // have to be on a power of two boundary. + // BUT: UC and WB types are allowed to overlap. + // so there is no problem with letting MTRR 0 overlap MTRR 1 + printk(KERN_INFO "set_mtrr: rambase is 0x%x, ramsizeK is 0x%x\n", + rambase, ramsizeK); +#if 0 +// why doesn't this work! machine hangs! + printk(KERN_INFO "setting MTRR 0 size to 0x%x\n", + (ramsizeK + 4096) * 1024); + intel_set_var_mtrr(0, 0, (ramsizeK + 4096) * 1024, MTRR_TYPE_WRBACK); + intel_set_var_mtrr(1, (ramsizeK * 1024), + 4096 * 1024, MTRR_TYPE_UNCACHABLE); +#else + // Ollie, this is a hack! Sorry! Ron + printk(KERN_INFO "Setting 256M MTRR 0\n"); + intel_set_var_mtrr(0, 0, 256 * 1024 * 1024, MTRR_TYPE_WRBACK); +#ifdef HAVE_FRAMEBUFFER + // for SiS, ramsizeK is the base of the framebuffer. + // but if it's less than 60M, don't bother ... + if (ramsizeK > 60*1024) + { + printk(KERN_INFO "Setting %dM, 4M size MTRR 1\n", + ramsizeK); + intel_set_var_mtrr(1, ramsizeK * 1024, 4096 * 1024, + MTRR_TYPE_UNCACHABLE); + } +#endif + printk(KERN_INFO "MTRRs set\n"); +#endif #else printk("Setting variable MTRR 0 to %dK\n", ramsizeK); intel_set_var_mtrr(0, 0, ramsizeK * 1024, MTRR_TYPE_WRBACK); diff --git a/src/mainboard/intel/l440gx/mainboard.c b/src/mainboard/intel/l440gx/mainboard.c new file mode 100644 index 0000000000..a835d16c19 --- /dev/null +++ b/src/mainboard/intel/l440gx/mainboard.c @@ -0,0 +1,179 @@ +#include +#include + +// this needs to be moved about a bit to northbridge.c etc. + + +void intel_mainboard_fixup() +{ + struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev; + unsigned smbus_io, pm_io; + unsigned int i, j; + printk("intel_mainboard_fixup()\n"); + +#if 1 + pm_pcidev = pci_find_device(0x8086, 0x7113, 0); + nic_pcidev = pci_find_device(0x8086, 0x1229, 0); + host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0)); +#endif +#if 1 + pci_write_config_byte(nic_pcidev, 0x3c, 21); +#endif +#if 1 + { + unsigned char byte; + unsigned short word; + unsigned long dword; + for(i = 0; i < 8; i++) { + pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte); + printk("DRB[i] = 0x%02x\n", byte); + } + pci_read_config_byte(host_bridge_pcidev, 0x57, &byte); + printk("DRAMC = 0x%02x\n", byte); + pci_read_config_byte(host_bridge_pcidev, 0x74, &byte); + printk("RPS = 0x%02x\n", byte); + pci_read_config_word(host_bridge_pcidev, 0x78, &word); + printk("PGPOL = 0x%04x\n", word); + pci_read_config_dword(host_bridge_pcidev, 0x50, &dword); + printk("NBXCFG = 0x%04x\n", dword); + } + +#endif +#if 1 + + printk("Reset Control Register\n"); + outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9); + + printk("port 92\n"); + outb((inb(0x92) & 0xFE), 0x92); + + printk("Disable Nmi\n"); + outb(0, 0x70); + + printk("enabling smbus\n"); +#if 0 + smbus_io = NewPciIo(0x10); +#else + smbus_io = 0xFFF0; +#endif + pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */ + pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */ + pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */ + + + printk("enable pm functions\n"); +#if 0 + pm_io = NewPciIo(0x40); +#else + pm_io = 0xFF80; +#endif + pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */ + pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */ + + printk("disabling smi\n"); + /* GLBEN */ + outw(0x00, pm_io + 0x20); + /* GLBCTL */ + outl((1 << 24), pm_io + 0x28); + + printk("Disable more pm stuff\n"); + /* PMEN */ + outw((1 << 8), pm_io + 0x02); + /* PMCNTRL */ + outw((0x5 << 10) , pm_io + 0x4); + /* PMTMR */ + outl(0, pm_io + 0x08); + /* GPEN */ + outw(0, pm_io + 0x0e); + /* PCNTRL */ + outl(0, pm_io + 0x10); + /* GLBSTS */ + /* DEVSTS */ + /* GLBEN see above */ + /* GLBCTL see above */ + /* DEVCTL */ + outl(0, pm_io + 0x2c); + /* GPIREG */ + /* GPOREG */ + + printk("Set the subsystem vendor id\n"); + pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086); + + printk("Disabling pm stuff in pci config space\n"); + +#define MAX_COUNTERS +#ifndef MAX_COUNTERS + /* counters to 0 */ +#define WHICH_COUNTERS(min,max) min +#else + /* max out the counters */ +#define WHICH_COUNTERS(min,max) max +#endif + + /* CNTA */ + pci_write_config_dword(pm_pcidev, 0x44, WHICH_COUNTERS(0x004000f0, 0xFFFFFFFF)); + + /* CNTB */ + pci_write_config_dword(pm_pcidev, 0x48, WHICH_COUNTERS(0x00000400, 0x007c07df)); + + /* GPICTL */ + pci_write_config_dword(pm_pcidev, 0x4c, 0); + + /* DEVRESD */ + pci_write_config_dword(pm_pcidev, 0x50, 0); + + /* DEVACTA */ + pci_write_config_dword(pm_pcidev, 0x54, 0); + + /* DEVACTB */ + pci_write_config_dword(pm_pcidev, 0x58, 0); + + /* DEVRESA */ + pci_write_config_dword(pm_pcidev, 0x5c, 0); + + /* DEVRESB */ + pci_write_config_dword(pm_pcidev, 0x60, 0); + + /* DEVRESC */ + pci_write_config_dword(pm_pcidev, 0x64, 0); /* might kill the serial port */ + + /* DEVRESE */ + pci_write_config_dword(pm_pcidev, 0x68, 0); + + /* DEVRESF */ + pci_write_config_dword(pm_pcidev, 0x6c, 0); + + /* DEVRESG */ + pci_write_config_dword(pm_pcidev, 0x70, 0); + + /* DEVRESH */ + pci_write_config_dword(pm_pcidev, 0x74, 0); + + /* DEVRESI */ + pci_write_config_dword(pm_pcidev, 0x78, 0); + + /* DEVRESJ */ + pci_write_config_dword(pm_pcidev, 0x7c, 0); + +#endif + +#if 1 + + /* Verify that smi is disabled */ + printk("Testing SMI\r\n"); + { + u32 value; + pci_read_config_dword(pm_pcidev, 0x58, &value); + pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25)); + } + outb(inb(0xb2), 0xb2); + printk("SMI disabled\r\n"); +#endif +#if 0 + + for(i = 0; i < 255; i++) { + printk("%08x\r\n", i); + __rdtsc_delay2(1000000000UL, pm_io); + } +#endif +} diff --git a/src/northsouthbridge/sis/630/ipl.S b/src/northsouthbridge/sis/630/ipl.S index 5d54eb3903..263ccc37ef 100644 --- a/src/northsouthbridge/sis/630/ipl.S +++ b/src/northsouthbridge/sis/630/ipl.S @@ -164,11 +164,17 @@ no_sdram: movw %fs, %ax movb $0x63, %ah - +#ifdef HAVE_FRAMEBUFFER orb $0x90, %al # enable SMA 4 MB for VGA +#endif #else /* SIZE_ALL */ no_sdram: +#ifdef HAVE_FRAMEBUFFER + # enable DIMM 0 and movw $0x6391, %ax # enable SMA 4 MB for VGA +#else + movw $0x6301, %ax # enable DIMM 0 +#endif // HAVE_FRAMEBUFFER #endif /* SIZE_ALL */ CALL_SP(write_pci_register) # write register 0x63 diff --git a/src/southbridge/intel/piix4e/southbridge.c b/src/southbridge/intel/piix4e/southbridge.c new file mode 100644 index 0000000000..da97da2f02 --- /dev/null +++ b/src/southbridge/intel/piix4e/southbridge.c @@ -0,0 +1,8 @@ +#include +#include +#include + +void +southbridge_fixup() +{ +}