diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
index 954ec712e0..affde9dce4 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
+++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c
@@ -179,15 +179,15 @@ static const struct pad_config wwan_disable_pads[] = {
 
 /* Gen4 NVME: at the top M.2 slot */
 static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = {
-	/* GPP_B10:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B10, 0, PLTRST),
+	/* GPP_H18:     EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_H18, 0, PLTRST),
 };
 
 static const struct pad_config gen4_ssd_pads[] = {
-	/* GPP_B10:     GEN4_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B10, 1, PLTRST),
-	/* GPP_B09:     M2_GEN4_SSD_RESET_N */
-	PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+	/* GPP_B10:     EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_H18, 1, PLTRST),
+	/* GPP_B09:     SSD_PERST_L */
+	PAD_CFG_GPO(GPP_A08, 1, PLTRST),
 };
 
 static const struct pad_config ufs_enable_pads[] = {
@@ -195,19 +195,6 @@ static const struct pad_config ufs_enable_pads[] = {
 	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 };
 
-/* Gen5 NVME: at the bottom M.2 slot */
-static const struct pad_config pre_mem_gen5_ssd_pwr_pads[] = {
-	/* GPP_B16:     GEN5_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B16, 0, PLTRST),
-};
-
-static const struct pad_config gen5_ssd_pads[] = {
-	/* GPP_B16:     GEN5_SSD_PWREN */
-	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
-	/* GPP_E03:     M2_GEN5_SSD_RESET_N */
-	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
-};
-
 static const struct pad_config peg_x4slot_wake_disable_pads[] = {
 	/* GPP_D24:     PEG_SLOT_WAKE_N */
 	PAD_NC(GPP_D24, NONE),
@@ -459,11 +446,8 @@ void fw_config_configure_pre_mem_gpio(void)
 
 	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
 		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
-	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
-		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
 		GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads);
-		GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
 	}
 
 	/*
@@ -495,13 +479,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 
 	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
-	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) {
-		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
 	} else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) {
 		GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads);
-		GPIO_PADBASED_OVERRIDE(padbased_table, gen5_ssd_pads);
 		GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads);
 	}
 
diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
index f80ac8973a..e692c080c0 100644
--- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
+++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
@@ -34,8 +34,7 @@ fw_config
 	field STORAGE 13 14
 		option STORAGE_UNKNOWN		0
 		option STORAGE_NVME_GEN4	1
-		option STORAGE_NVME_GEN5	2
-		option STORAGE_UFS		3
+		option STORAGE_UFS		2
 	end
 	field FP 15
 		option FP_ABSENT		0
@@ -546,8 +545,8 @@ chip soc/intel/pantherlake
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "is_storage" = "true"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
 				register "srcclk_pin" = "6"
 				device generic 0 on end
 			end