diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig
index e0efc9a987..8a3adf58d7 100644
--- a/src/soc/qualcomm/common/Kconfig
+++ b/src/soc/qualcomm/common/Kconfig
@@ -6,6 +6,12 @@ config SOC_QUALCOMM_COMMON
 	help
 	  Selected by platforms that use the common code.
 
+config QC_COMMON_QUPV3_2
+	bool
+	default n
+	help
+	  Selected by chipsets that has QUPv3 HW Version 2.
+
 if SOC_QUALCOMM_COMMON
 
 config QC_SDI_ENABLE
diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index 09484b76f4..cd700a3224 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -128,8 +128,15 @@ void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg,
 	unsigned int idx, s = qup % QUP_WRAP1_S0;
 	uint32_t reg_val;
 
-	qup_clk = qup < QUP_WRAP1_S0 ?
-				&gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s];
+#if QUP_WRAP2_BASE
+	if (qup >= QUP_WRAP2_S0)
+		qup_clk = &gcc->qup_wrap2_s[s];
+	else
+#endif
+	if (qup >= QUP_WRAP1_S0)
+		qup_clk = &gcc->qup_wrap1_s[s];
+	else
+		qup_clk = &gcc->qup_wrap0_s[s];
 
 	clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr,
 			BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT),
diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index b08d39bdd8..2c127429e1 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -45,6 +45,9 @@ struct clock_freq_config {
 
 struct qupv3_clock {
 	u32 cbcr;
+#if CONFIG(QC_COMMON_QUPV3_2)
+	u8 _res0[0x08];
+#endif
 	struct clock_rcg_mnd clk;
 	struct clock_rcg_dfsr dfsr_clk;
 };